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(10) PF0 to PF3 … PWM output waveform frame frequency setting control data
These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the f
CK
2 = 38[kHz] typ (EXF = "1") in external clock operating mode (OC = "1"), these control data bits
become invalid.
Control data PWM output waveform frame frequency fp[Hz]
PF0 PF1 PF2 PF3
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz] typ)
External clock operating mode
(The control data OC is 1 and EXF is 0,
f
CK
1=300[kHz] typ)
0 0 0 0 fosc/1536 f
CK
1/1536
1 0 0 0 fosc/1408 f
CK
1/1408
0 1 0 0 fosc/1280 f
CK
1/1280
1 1 0 0 fosc/1152 f
CK
1/1152
0 0 1 0 fosc/1024 f
CK
1/1024
1 0 1 0 fosc/896 f
CK
1/896
0 1 1 0 fosc/768 f
CK
1/768
1 1 1 0 fosc/640 f
CK
1/640
0 0 0 1 fosc/512 f
CK
1/512
1 0 0 1 fosc/384 f
CK
1/384
0 1 0 1 fosc/256 f
CK
1/256
Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame
frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, f
CK
1/896).
X: don’t care
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(11) W10 to W15, W20 to W25, W30 to W35 … PWM data of the PWM output
These control data bits set the pulse width of the PWM output P1 to P4. However, when the PWM output function
isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the
f
CK
2 = 38[kHz] typ (EXF = "1") in external clock operating mode (OC = "1"), these control data bits become
invalid.
Wn0 Wn1 Wn2 Wn3 Wn4 Wn5
Pulse width of
PWM output
Wn0 Wn1 Wn2 Wn3 Wn4 Wn5
Pulse width of
PWM output
0 0 0 0 0 0 (1/64)×Tp 0 0 0 0 0 1 (33/64)×Tp
1 0 0 0 0 0 (2/64)×Tp 1 0 0 0 0 1 (34/64)×Tp
0 1 0 0 0 0 (3/64)×Tp 0 1 0 0 0 1 (35/64)×Tp
1 1 0 0 0 0 (4/64)×Tp 1 1 0 0 0 1 (36/64)×Tp
0 0 1 0 0 0 (5/64)×Tp 0 0 1 0 0 1 (37/64)×Tp
1 0 1 0 0 0 (6/64)×Tp 1 0 1 0 0 1 (38/64)×Tp
0 1 1 0 0 0 (7/64)×Tp 0 1 1 0 0 1 (39/64)×Tp
1 1 1 0 0 0 (8/64)×Tp 1 1 1 0 0 1 (40/64)×Tp
0 0 0 1 0 0 (9/64)×Tp 0 0 0 1 0 1 (41/64)×Tp
1 0 0 1 0 0 (10/64)×Tp 1 0 0 1 0 1 (42/64)×Tp
0 1 0 1 0 0 (11/64)×Tp 0 1 0 1 0 1 (43/64)×Tp
1 1 0 1 0 0 (12/64)×Tp 1 1 0 1 0 1 (44/64)×Tp
0 0 1 1 0 0 (13/64)×Tp 0 0 1 1 0 1 (45/64)×Tp
1 0 1 1 0 0 (14/64)×Tp 1 0 1 1 0 1 (46/64)×Tp
0 1 1 1 0 0 (15/64)×Tp 0 1 1 1 0 1 (47/64)×Tp
1 1 1 1 0 0 (16/64)×Tp 1 1 1 1 0 1 (48/64)×Tp
0 0 0 0 1 0 (17/64)×Tp 0 0 0 0 1 1 (49/64)×Tp
1 0 0 0 1 0 (18/64)×Tp 1 0 0 0 1 1 (50/64)×Tp
0 1 0 0 1 0 (19/64)×Tp 0 1 0 0 1 1 (51/64)×Tp
1 1 0 0 1 0 (20/64)×Tp 1 1 0 0 1 1 (52/64)×Tp
0 0 1 0 1 0 (21/64)×Tp 0 0 1 0 1 1 (53/64)×Tp
1 0 1 0 1 0 (22/64)×Tp 1 0 1 0 1 1 (54/64)×Tp
0 1 1 0 1 0 (23/64)×Tp 0 1 1 0 1 1 (55/64)×Tp
1 1 1 0 1 0 (24/64)×Tp 1 1 1 0 1 1 (56/64)×Tp
0 0 0 1 1 0 (25/64)×Tp 0 0 0 1 1 1 (57/64)×Tp
1 0 0 1 1 0 (26/64)×Tp 1 0 0 1 1 1 (58/64)×Tp
0 1 0 1 1 0 (27/64)×Tp 0 1 0 1 1 1 (59/64)×Tp
1 1 0 1 1 0 (28/64)×Tp 1 1 0 1 1 1 (60/64)×Tp
0 0 1 1 1 0 (29/64)×Tp 0 0 1 1 1 1 (61/64)×Tp
1 0 1 1 1 0 (30/64)×Tp 1 0 1 1 1 1 (62/64)×Tp
0 1 1 1 1 0 (31/64)×Tp 0 1 1 1 1 1 (63/64)×Tp
1 1 1 1 1 0 (32/64)×Tp 1 1 1 1 1 1 (64/64)×Tp
Note: W10 to W15 … PWM data of the output pin S1/P1 and S4/P4
W20 to W25 … PWM data of the output pin S2/P2
W30 to W35 … PWM data of the output pin S3/P3
1
fp
Tp=
n=1 to 3
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Display Data and Output Pin Correspondence (1/4 Duty)
Output pin COM1 COM2 COM3 COM4
Output pin COM1 COM2 COM3 COM4
S1/P1 D1 D2 D3 D4 S27 D105 D106 D107 D108
S2/P2 D5 D6 D7 D8 S28 D109 D110 D111 D112
S3/P3 D9 D10 D11 D12 S29 D113 D114 D115 D116
S4/P4 D13 D14 D15 D16 S30 D117 D118 D119 D120
S5 D17 D18 D19 D20 S31 D121 D122 D123 D124
S6 D21 D22 D23 D24 S32 D125 D126 D127 D128
S7 D25 D26 D27 D28 S33 D129 D130 D131 D132
S8 D29 D30 D31 D32 S34 D133 D134 D135 D136
S9 D33 D34 D35 D36 S35 D137 D138 D139 D140
S10 D37 D38 D39 D40 S36 D141 D142 D143 D144
S11 D41 D42 D43 D44 S37 D145 D146 D147 D148
S12 D45 D46 D47 D48 S38 D149 D150 D151 D152
S13 D49 D50 D51 D52 S39 D153 D154 D155 D156
S14 D53 D54 D55 D56 S40 D157 D158 D159 D160
S15 D57 D58 D59 D60 S41 D161 D162 D163 D164
S16 D61 D62 D63 D64 S42 D165 D166 D167 D168
S17 D65 D66 D67 D68 S43 D169 D170 D171 D172
S18 D69 D70 D71 D72 S44 D173 D174 D175 D176
S19 D73 D74 D75 D76 S45 D177 D178 D179 D180
S20 D77 D78 D79 D80 S46 D181 D182 D183 D184
S21 D81 D82 D83 D84 S47 D185 D186 D187 D188
S22 D85 D86 D87 D88 S48 D189 D190 D191 D192
S23 D89 D90 D91 D92 S49 D193 D194 D195 D196
S24 D93 D94 D95 D96 S50 D197 D198 D199 D200
S25 D97 D98 D99 D100 S52 D201 D202 D203 D204
S26 D101 D102 D103 D104 S53/OSCI D205 D206 D207 D208
Note: This table assumes that pins S1/P1 to S4/P4 and S53/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81 D82 D83 D84
0 0 0 0 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0 0 0 1 The LCD segment corresponding to COM4 is on.
0 0 1 0 The LCD segment corresponding to COM3 is on.
0 0 1 1 The LCD segments corresponding to COM3 and COM4 are on.
0 1 0 0 The LCD segment corresponding to COM2 is on.
0 1 0 1 The LCD segments corresponding to COM2 and COM4 are on.
0 1 1 0 The LCD segments corresponding to COM2 and COM3 are on.
0 1 1 1 The LCD segments corresponding to COM2, COM3, and COM4 are on.
1 0 0 0 The LCD segment corresponding to COM1 is on.
1 0 0 1 The LCD segments corresponding to COM1 and COM4 are on.
1 0 1 0 The LCD segments corresponding to COM1 and COM3 are on.
1 0 1 1 The LCD segments corresponding to COM1, COM3, and COM4 are on.
1 1 0 0 The LCD segments corresponding to COM1 and COM2 are on.
1 1 0 1 The LCD segments corresponding to COM1, COM2, and COM4 are on.
1 1 1 0 The LCD segments corresponding to COM1, COM2, and COM3 are on.
1 1 1 1 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.

LC75839PWS-H

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LCD Drivers LCD DISPLAY DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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