SSTUB32864AHLFT Datasheet SSTUB32864AHLFT, SSTUB32864AHLF | P7-P9

ICSSSTUB32864A

Advance Information

1166—10/05/05

7

Electrical Characteristics - DC

T

A

= 0 - 70°C; V

DD

= 1.8 +/-0.1V (unless otherwise stated)

SYMBOL PARAMETERS V

DD

MIN TYP MAX UNITS

V

IK

I

= -18mA -1.2

V

OH

I

OH

= -6mA 1.7V 1.2

V

OL

I

OL

= 6mA 1.7V 0.5

I

All Inputs V

I

= V

DD

or GND 1.9V -5 5 µA

Standby (Static) RESET# = GND 100 µA

Operating (Static)

V

I

= V

IH(AC)

or V

IL(AC)

,

RESET# = V

DD

40 mA

Dynamic operating

(clock only)

RESET# = V

DD

,

V

I

= V

IH(AC)

or V

IL(AC)

,

CLK and CLK# switching

50% duty cycle.

39

µ/clock

MHz

Dynamic Operating

(per each data input)

1:1 mode

19

Dynamic Operating

(per each data input)

1:2 mode

35

Data Inputs 2.5 3.5

CLK and CLK# 2 3

RESET# 2.5

Notes:

1 - Guaranteed by design, not 100% tested in production.

C

i

V

I

= V

DD

or GND

I

DDD

RESET# = V

DD

,

V

I

= V

IH(AC)

or V

IL (AC)

,

CLK and CLK# switching

50% duty cycle. One data

input switching at half

clock frequency, 50%

dut

y

c

y

cle

I

O

= 0

I

DD

CONDITIONS

V

I

= V

REF

±350mV

V

ICR

= 1.25V, V

I

(

PP

)

= 360mV

pF

µA/ clock

MHz/data

V

1.9V

1.8V

ICSSSTUB32864A

Advance Information

1166—10/05/05

8

Timing Requirements

(over recommended operating free-air temperature range, unless otherwise noted)

SYMBOL PARAMETERS

MIN MAX

UNITS

f

clock

Clock frequency 410 MHz

t

W

1ns

t

ACT

10 ns

t

INACT

15 ns

Setup time

DCS before CK, CK↓,

CSR high; CSR before

CK, CK↓, DCS hi

g

h

0.6 ns

DCS before CK, CK↓,

CSR Low

0.5 ns

DODT, DCKE and data

before CK, CK↓

0.5 ns

DCS, DODT, DCKE and

data after CK, CK↓

0.4 ns

PAR_IN after CK, CK↓ 0.4 ns

1 - Guaranteed by design, not 100% tested in production.

2 - For data signal input slew rate of 1V/ns.

4 - CLK/CLK# signal input slew rate of 1V/ns.

Pulse duration, CK, CK High or Low

Differential inputs active time (See notes 1 and 2)

Differential inputs inactive time (See notes 1 and 3)

Hold time

t

SU

t

h

Notes:

3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.

Setup time

Switching Characteristics

(over recommended operating free-air temperature range, unless otherwise noted)

MIN TYP MAX

fmax 410 MHz

t

PDM

1

CLK, CLK# Q 1.1 1.5 ns

t

PDMSS

2

CLK, CLK# Q 1.6

t

phl

RESET# Q 3 ns

Notes: 1. Includes 350ps test-load transmission-line delay

2. Guaranteed by design, not 100% tested in production.

SYMBOL

V

DD

= 1.8V ±0.1V

UNITS

From

(

In

p

ut

)

To

(

Out

p

ut

)

Output Buffer Characteristics

Output ed

g

e rates over recommended operatin

g

free-air temperature ran

g

e (See fi

g

ure 7)

MIN MAX

dV/dt_r 1 4 V/ns

dV/dt_f 1 4 V/ns

dV/dt

_

∆

1

1V/ns

1. Difference between dV/dt_r (risin

g

ed

g

e rate) and dV/dt_f (fallin

g

ed

g

e rate)

PARAMETER

V

DD

= 1.8V ± 0.1V

UNIT

ICSSSTUB32864A

Advance Information

1166—10/05/05

9

Notes: 1. C

L

incluces probe and jig capacitance.

2. I

DD

tested with clock and data inputs held at V

DD

or GND, and Io = 0mA.

3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,

Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. V

REF

= V

DD

/2

6. V

IH

= V

REF

+ 250 mV (ac voltage levels) for differential inputs. V

IH

= V

DD

for LVCMOS input.

7. V

IL

= V

REF

- 250 mV (ac voltage levels) for differential inputs. V

IL

= GND for LVCMOS input.

8. V

ID

= 600 mV

9. t

PLH

and t

PHL

are the same as t

PDM

.

Figure 6 — Parameter (V

DD

= 1. 8 V ± 0.1 V)

R

L

= 1000Ω

C

L

= 30 pF

(see Note 1)

LOAD CIRCUIT

t

w

V

ICR

V

ICR

Inpu t

V

IH

V

IL

VOLTAGE WAVEFORMS – PULSE DURATION

V

REF

V

REF

Inpu t

t

su

t

h

V

ID

V

ICR

VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES

V

ICR

V

ID

V

ICR

Output

V

OL

V

OH

V

TT

V

TT

t

PHL

t

PLH

VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES

t

RPHL

V

OL

V

OH

V

IL

V

IH

Output

VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES

V

DD

/2

V

TT

t

act

t

inact

LV CMOS

Input

RST#

VOLTAGE AND CURRENT WAVEFORMS

I

DD

(see

Note 2)

90%

10%

INPUTS ACTIVE AND INACTIVE TIMES

0 V

V

DD

Tes t Po i nt

V

DD

/2 V

DD

/2

VCMOS

Inp ut

RST#

TL=350ps, 50Ω

DUT

CK#

Out

TL=50Ω

CK Inputs

V

ID

CK

R

L

= 100Ω

CK

Tes t Po i nt

R

L

= 1000Ω

V

DD

Measurement Information

SSTUB32864AHLFT

SSTUB32864AHLFT

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