DS1882
Dual Log Audio Digital Potentiometer
____________________________________________________________________ 13
setup time (see Figure 4) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse, and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses, including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
(Figure 4) for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
12 678 9 12 893–7
Figure 3. Data Transfer Protocol
SDA
SCL
t
HD:STA
t
LOW
t
HIGH
t
R
t
F
t
HD:DAT
t
SU:DAT
REPEATED
START
t
SU:STA
t
HD:STA
t
SU:STO
t
SP
STOP START
t
BUF
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
IH(MIN)
.
Figure 4. I
2
C Timing Diagram
DS1882
Dual Log Audio Digital Potentiometer
14 ____________________________________________________________________
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave will return control of SDA to
the master.
Slave Address Byte: Each slave on the I
2
C bus
responds to a slave addressing byte sent immediately
following a START condition. The slave address byte
(Figure 5) contains the slave address in the most signif-
icant 7 bits and the R/W bit in the least significant bit.
The DS1882s slave address is 0101 A2 A1 A0 (binary),
where A2, A1, and A0 are the values of the address
pins. The address pins allow the device to respond to
one of eight possible slave addresses. By writing the
correct slave address with R/W = 0, the master indi-
cates it will write data to the slave. If R/W = 1, the mas-
ter will read data from the slave. If an incorrect slave
address is written, the DS1882 will assume the master is
communicating with another I
2
C device and ignore the
communications until the next START condition is sent.
I
2
C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the byte of data, and generate a
STOP condition. The master must read the slaves
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
desired number of data bytes and generates a STOP
condition. The DS1882 is capable of writing both poten-
tiometer wiper settings and the Configuration Register
with a single write transaction.
Acknowledge Polling: Any time an EEPROM location
is written, the DS1882 requires the EEPROM write time
(t
W
) after the STOP condition to write the contents of
the byte of data to EEPROM. During the EEPROM write
time, the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS1882, which allows the next page to be written as
soon as the DS1882 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
mum period of t
W
to elapse before attempting to write
again to the device.
EEPROM Write Cycles: When EEPROM writes occur to
the memory, the DS1882 will write to all three EEPROM
memory locations, even if only a single byte was modi-
fied. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte repeat-
edly. The DS1882s EEPROM write cycles are specified in
the NV Memory Characteristics table. The specification
shown is at the worst-case temperature. If zero-crossing
detection is enabled, EEPROM write cycles cannot begin
until after the zero-crossing detection is complete.
Reading a Single Byte from a Slave: To read a single
byte from the slave, the master generates a START con-
dition, writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition. When a single
byte is read, it will always be the Potentiometer 0 value.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte, it NACKs to indicate the end of
the transfer and generates a STOP condition. The first
byte read will be the Potentiometer 0 Wiper Setting. The
next byte will be the Potentiometer 1 Wiper Setting. The
third byte is the Configuration Register byte. If an ACK
is issued by the master following the Configuration
Register byte, then the DS1882 will send the
Potentiometer 0 Wiper Setting again. This round robin
reading will occur as long as each byte read is followed
by an ACK from the master.
0
MSB
7-BIT SLAVE
ADDRESS
DETERMINES
READ OR WRITE
FUNCTION
A2, A1, AND A0
PIN VALUES
LSB
101
A2
A1 A0 R/W
Figure 5. DS1882s Slave Address Byte
DS1882
Dual Log Audio Digital Potentiometer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Springer
Applications Information
Power-Supply Decoupling
To achieve best results, it is recommended that the
power supplies are decoupled with a 0.01µF or a 0.1µF
capacitor. Use high-quality, ceramic, surface-mount
capacitors, and mount the capacitors as close as pos-
sible to the voltage supplies and GND pins to minimize
lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS1882 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be uti-
lized for SCL. Pullup resistor values should be chosen
to ensure that the rise and fall times listed in the AC
Electrical Characteristics table are within specification.
SCL
SDA
GND
V
DD
V
CC
H1
H0
W1
W0
L1
L0
A1
A0
A2
AUDIO
OUT
CE
DECOUPLING
CAPACITOR
DECOUPLING
CAPACITOR
4.7k
4.7k
HOST
µC
AUDIO IN
5V (V
CC
)
5V (V
DD
)
DS1882
-5V (V-)
V-
DECOUPLING
CAPACITOR
Typical Operating Circuit
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo
.
Chip Topology
TRANSISTOR COUNT: 52,353
SUBSTRATE CONNECTED TO GROUND

DS1882E-050+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital Potentiometer ICs Dual NV Audio Taper
Lifecycle:
New from this manufacturer.
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