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XC18V512SO20I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
XC18V00 Series In-System Programmable Configuration PROMs
4 www.xilinx.com DS026 (v4.1) December 15, 2003
1-800-255-7778 Product Specification
R
Pinout Diagrams
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
PC44
Top View
NC
NC
TDO
NC
D1
GND
D3
V
D5
NC
NC
CCO
NC
OE/RESET
D6
CE
V
CCO
VCCINT*
GND
D7
NC
CEO
NC
NC
NC
TDI
NC
TMS
GND
TCK
V
D4
CF
NC
CCO
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
V
CCO
VCCINT*
NC
DS026_12_060403
*See pin descriptions.
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
NC
NC
TDO
NC
D1
GND
D3
V
D5
NC
NC
CCO
NC
OE/RESET
D6
CE
V
CCO
VCCINT*
GND
D7
NC
CEO
NC
NC
NC
TDI
NC
TMS
GND
TCK
V
D4
CF
NC
CCO
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
V
CCO
VCCINT*
NC
DS026_13_060403
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
*See pin descriptions.
SO20
Top
View
DS026_14_060403
*See pin descriptions.
1
2
3
4
5
6
7
8
9
10
DATA(D0)
D2
CLK
TDI
TMS
TCK
CF/D4*
OE/RESET
D6
CE
20
19
18
17
16
15
14
13
12
11
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
CEO
D7
GND
PC20
Top View
DS026_15_060403
3
2
1
20
19
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
CLK
D2
D0
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
D6
CE
GND
D7
CEO
TDI
TMS
TCK
D4/CF*
OE/RESET
*See pin descriptions.
XC18V00 Series In-System Programmable Configuration PROMs
DS026 (v4.1) December 15, 2003 www.xilinx.com 5
Product Specification 1-800-255-7778
R
Xilinx FPGAs and Compatible PROMs
Table 2 provides a list of Xilinx FPGAs and compatible
PROMs.
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
XC2VP2 1,305,440 XC18V02
XC2VP4 3,006,560 XC18V04
XC2VP7 4,485,472 XC18V04 +
XC18V512
XC2VP20 8,214,624 2 of XC18V04
XC2VP30 11,364,608 3 of XC18V04
XC2VP40 15,563,264 4 of XC18V04
XC2VP50 19,021,472 5 of XC18V04
XC2VP70 25,604,096 6 of XC18V04 +
XC18V512
XC2VP100 33,645,312 8 of XC18V04 +
XC18V512
XC2VP125 42,782,208 10 of XC18V04 +
XC18V01
XC2V40 360,096 XC18V512
XC2V80 635,296 XC18V01
XC2V250 1,697,184 XC18V02
XC2V500 2,761,888 XC18V04
XC2V1000 4,082,592 XC18V04
XC2V1500 5,659,296 XC18V04
+ XC18V02
XC2V2000 7,492,000 2 of XC18V04
XC2V3000 10,494,368 3 of XC18V04
XC2V4000 15,659,936 4 of XC18V04
XC2V6000 21,849,504 5 of XC18V04 +
XC18V02
XC2V8000 29,063,072 7 of XC18V04
XCV50 559,200 XC18V01
XCV100 781,216 XC18V01
XCV150 1,040,096 XC18V01
XCV200 1,335,840 XC18V02
XCV300 1,751,808 XC18V02
XCV400 2,546,048 XC18V04
XCV600 3,607,968 XC18V04
XCV800 4,715,616 XC18V04 +
XC18V512
XCV1000 6,127,744 XC18V04 +
XC18V02
XCV50E 630,048 XC18V01
XCV100E 863,840 XC18V01
XCV200E 1,442,016 XC18V02
XCV300E 1,875,648 XC18V02
XCV400E 2,693,440 XC18V04
XCV405E 3,430,400 XC18V04
XCV600E 3,961,632 XC18V04
XCV812E 6,519,648 2 of XC18V04
XCV1000E 6,587,520 2 of XC18V04
XCV1600E 8,308,992 2 of XC18V04
XCV2000E 10,159,648 3 of XC18V04
XCV2600E 12,922,336 4 of XC18V04
XCV3200E 16,283,712 4 of XC18V04
XC2S15 197,696 XC18V512
XC2S30 336,768 XC18V512
XC2S50 559,200 XC18V01
XC2S100 781,216 XC18V01
XC2S150 1,040,096 XC18V01
XC2S200 1,335,840 XC18V02
XC2S50E 630,048 XC18V01
XC2S100E 863,840 XC18V01
XC2S150E 1,134,496 XC18V02
XC2S200E 1,442,016 XC18V02
XC2S300E 1,875,648 XC18V02
XC2S400E 2,693,440 XC18V04
XC2S600E 3,961,632 XC18V04
XC3S50 439,264 XC18V512
XC3S200 1,047,616 XC18V01
XC3S400 1,699,136 XC18V02
XC3S1000 3,223,488 XC18V04
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
XC18V00 Series In-System Programmable Configuration PROMs
6 www.xilinx.com DS026 (v4.1) December 15, 2003
1-800-255-7778 Product Specification
R
Capacity
In-System Programming
In-System Programmable PROMs can be programmed
individually, or two or more can be daisy-chained together
and programmed in-system via the standard 4-pin JTAG
protocol as shown in Figure 2. In-system programming
offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
The Xilinx development system provides the programming
data sequence using either Xilinx iMPACT software and a
download cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format and with
automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
OE/RESET
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130, Xilinx MultiPRO, or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data reten-
tion specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incor-
porate advanced data security features to fully protect the
programming data against unauthorized reading via JTAG.
Table 3 shows the security setting available.
XC3S1500 5,214,784 XC18V04 +
XC18V01
XC3S2000 7,673,024 2 of XC18V04
XC3S4000 11,316,864 3 of XC18V04
XC3S5000 13,271,936 3 of XC18V04 +
XC18V01
Devices Configuration Bits
XC18V04 4,194,304
XC18V02 2,097,152
XC18V01 1,048,576
XC18V512 524,288
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
DS026_02_06/1103
GND
V
CCINT
(a) (b)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

XC18V512SO20I

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Manufacturer:
Xilinx
Description:
IC PROM SER I-TEMP 3.3V 20-SOIC
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