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74AHC2G00DP-Q100H

P1-P3P4-P6P7-P9P10-P12P13-P15
74AHC_AHCT2G00_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 21 March 2013 9 of 14
NXP Semiconductors 74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
13. Package outline
Fig 7. Package outline SOT505-2 (TSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(1)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.70
0.35
8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - -
02-01-16
w M
b
p
D
Z
e
0.25
14
8
5
θ
A
2
A
1
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
1.1
pin 1 index
74AHC_AHCT2G00_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 21 March 2013 10 of 14
NXP Semiconductors 74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
Fig 8. Package outline SOT765-1 (VSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(2)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187
02-06-07
w M
b
p
D
Z
e
0.12
14
8
5
θ
A
2
A
1
Q
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index
74AHC_AHCT2G00_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 21 March 2013 11 of 14
NXP Semiconductors 74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
MIL Military
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT2G00_Q100 v.1 20130321 Product data sheet - -
P1-P3P4-P6P7-P9P10-P12P13-P15

74AHC2G00DP-Q100H

Mfr. #:
Buy 74AHC2G00DP-Q100H
Manufacturer:
Nexperia
Description:
Logic Gates 74AHC2G00DP-Q100/TSSOP8/REEL 7
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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