FST3306MTCX

© 2001 Fairchild Semiconductor Corporation DS500479 www.fairchildsemi.com
February 2001
Revised February 2001
FST3306 2-Bit Low Power Bus Switch
FST3306
2-Bit Low Power Bus Switch
General Description
The FST3306 is a 2-bit ultra high-speed CMOS FET bus
switch with TTL-compatible active LOW control inputs. The
low on resistance of the switch allows inputs to be con-
nected to outputs with minimal propagation delay and with-
out generating additional ground bounce noise. The device
is organized as a 2-bit switch with independent bus enable
(BE
) controls. When BE is LOW, the switch is ON and
Port A is connected to Port B. When BE
is HIGH, the
switch is OPEN and a high-impedance state exists
between the two ports. Control inputs tolerate voltages up
to 5.5V independent of V
CC
.
Features
Typical 3 switch resistance at 5.0V V
CC
Minimal propagation delay through the switch
Power down high impedance input/output
Zero bounce in flow through mode.
TTL compatible active LOW control inputs
Control inputs are overvoltage tolerant
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol Connection Diagram
(Top View)
Pin Descriptions Function Table
H = HIGH Logic Level
L = LOW Logic Level
Order Number Package Number Package Description
FST3306MTC MTC08 8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name Description
ABus A
BBus B
BE
Bus Enable Input
Bus Enable Input BE Function
L B Connected to A
H Disconnected
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FST3306
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused logic inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the volt-
ages on the two (A or B) pins.
Note 5: Per TTL driven input (V
IN
= 3.4V, control input only). A and B pins do not contribute to I
CC.
Supply Voltage (V
CC
) 0.5V to +7.0V
DC Switch Voltage (VS)
0.5V to +7.0V
DC Output Voltage (V
IN
) (Note 2) 0.5V to +7.0V
DC Input Diode Current
(I
IK
) V
IN
< 0V 50 mA
DC Output (I
OUT
) Current 128 mA
DC V
CC
or Ground Current (I
CC
/GND) ±100 mA
Storage Temperature Range (T
STG
) 65°C to +150°C
Junction Lead Temperature under Bias (T
J
) +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
+260°C
Power Dissipation (P
D
) @ +85°C 250 mW
Supply Operating (V
CC
) 4.0V to 5.5V
Control Input Voltage (V
IN
) 0V to 5.5V
Switch Input Voltage (V
IN
) 0V to 5.5V
Output Voltage (V
OUT
) 0V to 5.5V
Operating Temperature (T
A
) 40°C to +85°C
Input Rise and Fall Time (t
r
, t
f
)
Control Input 0 ns/V to 5 ns/V
Switch I/O 0 ns/V to DC
Thermal Resistance (
θ
JA
)250°C/W
Symbol Parameter
V
CC
T
A
= 40°C to +85°C
Units Conditions
(V) Min Typ Max
V
IK
Clamp Diode Voltage 4.5 1.2 V I
IN
= 18 mA
V
IH
HIGH Level Input Voltage 4.05.5 2.0 V
V
IL
LOW Level Input Voltage 4.05.5 0.8 V
V
OH
HIGH Level Output Voltage 4.55.5 see Figure 3 V V
IN
= V
CC
I
IN
Input Leakage Current 5.5 ±1.0 µA0 V
IN
5.5V
I
OFF
Switch OFF Leakage Current 5.5 ±1.0 µA0 A, B, V
CC
R
ON
Switch On Resistance 4.5 3 7
V
IN
= 0V, I
IN
= 64 mA
(Note 4) 4.5 3 7 V
IN
= 0V, I
IN
= 30 mA
4.5 6 15 V
IN
= 2.4V, I
IN
= 15 mA
4.0 10 20 V
IN
= 2.4V, I
IN
= 15 mA
I
CC
Quiescent Supply Current 5.5 3 µAV
IN
= V
CC
or GND,
I
OUT
= 0
I
CC
Increase in I
CC
per Input 5.5 1 2.5 mA V
IN
= 3.4V, I
O
= 0,
(Note 5) Control Input Only
3 www.fairchildsemi.com
FST3306
AC Electrical Characteristics
Note 6: This parameter is guaranteed. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch
and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). The specified limit is calculated on this basis.
Capacitance
AC Loading and Waveforms
Input driven by 50 source terminated in 50.
C
L
includes load and stray capacitance.
Input PRR = 1.0 MHz t
w
= 500 ns.
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
T
A
= 40°C to +85°C
Figure
Number
Symbol Parameter
V
CC
C
L
= 50 pF, RU = RD = 500
Units Conditions
(V) Min Typ Max
t
PHL
, Prop Delay Bus to Bus 4.05.5 0.25 ns V
I
= OPEN Figures
1, 2
t
PLH
(Note 6)
t
PZL
, Output Enable Time 4.55.5 0.8 2.5 4.2
ns
V
I
= 7V for t
PZL
Figures
1, 2
t
PZH
4.0 0.8 3.0 4.6 V
I
= 0V for t
PZH
t
PLZ
, Output Disable Time 4.55.5 0.8 3.1 4.8
ns
V
I
= 7V for t
PLZ
Figures
1, 2
t
PHZ
4.0 0.8 2.9 4.4 V
I
= 0V for t
PHZ
Symbol Parameter Typ Max Units Conditions
C
IN
Control Pin Input Capacitance 2.5 pF V
CC
= 0V
C
I/O
(OFF) Port OFF Capacitance 6 pF V
CC
= 5.0V = BE
C
I/O
(ON) Switch ON Capacitance 12 pF V
CC
= 5.0V, BE = 0V

FST3306MTCX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Digital Bus Switch ICs Low Power Bus Switch 2 Bit
Lifecycle:
New from this manufacturer.
Delivery:
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