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NCP1236AD100R2G

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NCP1236
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19
CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START
Current sensing
NCP1236 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. It is applied to one
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off.
The maximum value for the current sense is 0.7 V, and it
is set by a dedicated comparator.
CS
FB
−
+
t
LEB
blanking
K
FB
R
FB(up)
−
+
−
+
−
+
+
+
V
ILIM
V
CS(stop)
S
R
Q
t
SSTART
Soft−start ramp
Start
Reset
IC Start
IC Stop
Oscillator
DC
MAX
Protection
Mode
UVLO
Jitter
HV stop
Latch
Soft−start
IC stop
TSD
Fault
DRV Stage
blanking
PWM
t
BCS
Figure 36. Current Sense Block Schematic
V
FB(ref)
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when V
CC
reaches V
CC(on)
, a
soft−start is applied: the current sense setpoint is linearly
increased from 0 (the minimum level can be higher than 0
because of the LEB and propagation delay) until it reaches
V
ILIM
(after a duration of t
SSTART
), or until the FB loop
imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed). The
soft−start ramp signal is generated by the D/A converter in
the NCP1236, that’s why there are observable 15 discrete
steps instead the truly linearly increasing current setpoint
ramp.
NCP1236
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20
Time
V
FB
V
FB(fault)
Time
Soft-start ramp
V
ILIM
t
SSTART
Time
CS Setpoint
V
ILIMI
VFB takes
over soft-start
Figure 37. Soft−Start
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above V
ILIM
,
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
voltage on CS pin reaches V
CS(stop)
(= 1.5 x V
ILIM
), does:
as soon as this comparator toggles, the controller
immediately enters the protection mode (latched or
autorecovery according to the chosen option).
Overpower compensation
The power delivered by a flyback power supply is
proportional to the square of the peak current in the
discontinuous conduction mode:
P
OUT
+
1
2
@ h @ L
p
@ F
SW
@ I
p
2
(eq. 1)
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
NCP1236
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21
time
I
P
High
Line
Low
Line
I
LIMIT
t
delay
t
delay
I
P
to be
compensated
Figure 38. Line Compensation for True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than V
FB(OPCE)
.
However, because the HV pin can be connected to an ac
voltage, there is needed an additional circuitry to read or at
least closely estimate the actual voltage on the bulk
capacitor.
A/D 3 bit
Converter
+
Peak Detector
T
blanking
LEB
Watch
Dog
HV
CS
FB
V
HVstop
Q
QS
R
HV Timer
(68 ms)
(32 ms)
3 bit
Register
I Generator
Brown Out
t
hv
V
FB(OPC)
To CS
Block
I ctrl
Figure 39. Schematic Overpower Compensation Circuit
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the V
HV(stop)
comparator used for sampling detection for the AC line
input. If only the DC high voltage input is used, no reset
signal is generated by the V
HV(stop)
condition and the 32 ms
watch dog is used to generate the sampling events for
sampling the DC input high voltage line.
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NCP1236AD100R2G

Mfr. #:
Buy NCP1236AD100R2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers BRWN LATCH OCP OVP 100KHZ
Lifecycle:
New from this manufacturer.
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