The optically-coupled circuit of Figure 4.1
Si873x Input Circuit on page 7 turns the LED on when the control input is high. However,
internal capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off state when the
anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in Figure 4.2 High CMR Si873x Input
Circuit on page 7 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on during an
input common-mode transient. Q1 shorts the LED off in the low output state, again increasing common-mode transient immunity.
Some opto coupler applications recommend reverse-biasing the LED when the control input is off to prevent coupled noise from ener-
gizing the LED. The Si873x input circuit requires less current and has twice the off-state noise margin compared to opto couplers. How-
ever, high CMR opto coupler designs that overdrive the LED (see Figure 4.2 High CMR Si873x Input Circuit on page 7) may require
increasing the value of R1 to limit input current I
F
to its maximum rating when using the Si873x. In addition, there is no benefit in driving
the Si873x input diode into reverse bias when in the off state. Consequently, opto coupler circuits using this technique should either
leave the negative bias circuitry unpopulated or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that
the anode pin of the Si873x is no more than –0.3 V with respect to the cathode when reverse-biased.
New designs should consider the input circuit configurations of Figure 4.3 Si873x Other Input Circuit Configurations on page 8,
which are more efficient than those of the figures above. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOS-
FET, analog transmission gate, processor I/O, etc. Also, note that the Si873x input can be driven from the I/O port of any MCU or FPGA
capable of sourcing a minimum of 6 mA (see Figure 4.3 Si873x Other Input Circuit Configurations on page 8C). Additionally, note
that the Si873x propagation delay and output drive do not significantly change for values of I
F
between I
F(MIN)
and I
F(MAX)
.
Si873x
1
2
3
4
Vext
Control
Input
S1
N/C
ANODE
CATHODE
N/C
Si873x
B
C
R1
S2
4
N/C
3
CATHODE
2
MCU I/O
Port pin
ANODE
R1
1
N/C
Si873x
1
2
3
4
N/C
ANODE
CATHODE
N/C
A
R1
Control
Input
S1
See Text
Vext
Figure 4.3. Si873x Other Input Circuit Configurations
4.2 Output Circuit Design and Power Supply Connections
GND
can
be biased at, above, or below ground as long as the voltage on V
DD
with respect to GND is a maximum of 5.5 V. V
DD
decou-
pling capacitors should be placed as close to the package pins as possible. The optimum values for these capacitors depend on load
current and the distance between the chip and its power source. It is recommended that 0.1 and 1 µF bypass capacitors be used to
reduce high-frequency noise and maximize performance. Opto replacement applications should limit their supply voltages to 5.5 V or
less.
Si873x Data Sheet
Applications
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