15
ATF1504AS(L)
0950N–PLD–07/02
Output AC Test Loads
Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
Power-down Mode The ATF1504AS includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched internally and held. Therefore, all registered and
combinatorial output data remain valid. Any outputs that were in a high-Z state at the
onset will remain at high-Z. During power-down, all input signals except the power-down
pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float
to indeterminate levels, further reducing system power. The power-down mode feature
is enabled in the logic design file or as a fitted or translated s/w option. Designs using
the power-down pin may not use the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
Notes: 1. For slow slew outputs, add t
SSO
.
2. Pin or product term.
3. Includes t
RPA
due to reduced power bit enabled.
Power Down AC Characteristics
(1)(2)
Symbol Parameter
-7 -10 -15 -20 -25
UnitsMin Max Min Max Min Max Min Max Min Max
t
IVDH
ValidI,I/ObeforePDHigh 7 10152025 ns
t
GVDH
Valid OE
(2)
beforePDHigh 7 10152025 ns
t
CVDH
Valid Clock
(2)
beforePDHigh7 10152025 ns
t
DHIX
I, I/O Don’t Care after PD High 12 15 25 30 35 ns
t
DHGX
OE
(2)
Don’t Care after PD High 12 15 25 30 35 ns
t
DHCX
Clock
(2)
Don’t Care after PD High 12 15 25 30 35 ns
t
DLIV
PD Low to Valid I, I/O 1 1 1 1 1 µs
t
DLGV
PD Low to Valid OE (Pin or Term) 1 1 1 1 1 µs
t
DLCV
PD Low to Valid Clock (Pin or Term) 1 1 1 1 1 µs
t
DLOV
PD Low to Valid Output 1 1 1 1 1 µs
