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MJE13009

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 7
1 Publication Order Number:
MJE13009/D
MJE13009
Preferred Device
SWITCHMODEt Series
NPN Silicon Power
Transistors
The MJE13009 is designed for high−voltage, high−speed power
switching inductive circuits where fall time is critical. They are
particularly suited for 115 and 220 V SWITCHMODE applications
such as Switching Regulators, Inverters, Motor Controls,
Solenoid/Relay drivers and Deflection circuits.
Features
• V
CEO(sus)
400 V and 300 V
• Reverse Bias SOA with Inductive Loads @ T
C
= 100_C
• Inductive Switching Matrix 3 to 12 Amp, 25 and 100_C t
c
@ 8 A,
100_C is 120 ns (Typ)
• 700 V Blocking Capability
• SOA and Switching Applications Information
• Pb−Free Package is Available*
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector−Emitter Voltage V
CEO(sus)
400 Vdc
Collector−Emitter Voltage V
CEV
700 Vdc
Emitter−Base Voltage V
EBO
9 Vdc
Collector Current − Continuous
− Peak (Note 1)
I
C
I
CM
12
24
Adc
Base Current − Continuous
− Peak (Note 1)
I
B
I
BM
6
12
Adc
Emitter Current − Continuous
− Peak (Note 1)
I
E
I
EM
18
36
Adc
Total Device Dissipation @ T
C
= 25_C
Derate above 25°C
P
D
2
16
W
W/_C
Total Device Dissipation @ T
C
= 25_C
Derate above 25°C
P
D
100
800
W
W/_C
Operating and Storage Junction
Temperature Range
T
J
, T
stg
−65 to
+150
_C
THERMAL CHARACTERISTICS
Characteristics Symbol Max Unit
Thermal Resistance, Junction−to−Ambient
R
q
JA
62.5
_C/W
Thermal Resistance, Junction−to−Case
R
q
JC
1.25
_C/W
Maximum Lead Temperature for Soldering
Purposes 1/8″ from Case for 5 Seconds
T
L
275
_C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
12 AMPERE
NPN SILICON
POWER TRANSISTOR
400 VOLTS − 100 WATTS
TO−220AB
CASE 221A−09
STYLE 11
http://onsemi.com
MARKING DIAGRAM
2
3
MJE13009G
AY WW
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
Device Package Shipping
ORDERING INFORMATION
MJE13009 TO−220 50 Units / Rail
MJE13009G TO−220
(Pb−Free)
50 Units / Rail
Preferred devices are recommended choices for future use
and best overall value.
MJE13009
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS (T
C
= 25_C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS (Note 2)
Collector−Emitter Sustaining Voltage
(I
C
= 10 mA, I
B
= 0)
V
CEO(sus)
400 − − Vdc
Collector Cutoff Current
(V
CEV
= Rated Value, V
BE(off)
= 1.5 Vdc)
(V
CEV
= Rated Value, V
BE(off)
= 1.5 Vdc, T
C
= 100_C)
I
CEV
−
−
−
−
1
5
mAdc
Emitter Cutoff Current
(V
EB
= 9 Vdc, I
C
= 0)
I
EBO
− − 1 mAdc
SECOND BREAKDOWN
Second Breakdown Collector Current with base forward biased
Clamped Inductive SOA with Base Reverse Biased
I
S/b
−
See Figure 1
See Figure 2
ON CHARACTERISTICS (Note 2)
DC Current Gain
(I
C
= 5 Adc, V
CE
= 5 Vdc)
(I
C
= 8 Adc, V
CE
= 5 Vdc)
h
FE
8
6
−
−
40
30
Collector−Emitter Saturation Voltage
(I
C
= 5 Adc, I
B
= 1 Adc)
(I
C
= 8 Adc, I
B
= 1.6 Adc)
(I
C
= 12 Adc, I
B
= 3 Adc)
(I
C
= 8 Adc, I
B
= 1.6 Adc, T
C
= 100_C)
V
CE(sat)
−
−
−
−
−
−
−
−
1
1.5
3
2
Vdc
Base−Emitter Saturation Voltage
(I
C
= 5 Adc, I
B
= 1 Adc)
(I
C
= 8 Adc, I
B
= 1.6 Adc)
(I
C
= 8 Adc, I
B
= 1.6 Adc, T
C
= 100_C)
V
BE(sat)
−
−
−
−
−
−
1.2
1.6
1.5
Vdc
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product
(I
C
= 500 mAdc, V
CE
= 10 Vdc, f = 1 MHz)
f
T
4 − − MHz
Output Capacitance
(V
CB
= 10 Vdc, I
E
= 0, f = 0.1 MHz)
C
ob
− 180 − pF
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
(V
CC
= 125 Vdc, I
C
= 8 A,
I
B1
= I
B2
= 1.6 A, t
p
= 25 ms,
Duty Cycle v 1%)
t
d
− 0.06 0.1
ms
Rise Time t
r
− 0.45 1
ms
Storage Time t
s
− 1.3 3
ms
Fall Time t
f
− 0.2 0.7
ms
Inductive Load, Clamped (Table 1, Figure 13)
Voltage Storage Time
(I
C
= 8 A, V
clamp
= 300 Vdc,
I
B1
= 1.6 A, V
BE(off)
= 5 Vdc, T
C
= 100_C)
t
sv
− 0.92 2.3
ms
Crossover Time t
c
− 0.12 0.7
ms
2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
MJE13009
http://onsemi.com
3
I
C
, COLLECTOR CURRENT (AMP)
10m
σ
100m
σ
1m
s
dc
100
7
V
CE
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
0.02
10
20
10
50
0.5
0.1
0.05
30 50 70 100
Figure 1. Forward Bias Safe Operating Area
Figure 2. Reverse Bias Switching Safe
Operating Area
0.2
0.01
300 500520
14
0
800
2
100 300
T
C
≤ 100°C
I
B1
= 2.5 A
500 700
V
BE(off)
= 9 V
0
6
V
CEV
, COLLECTOR−EMITTER CLAMP VOLTAGE (VOLTS)
10
200 400 600
5 V
2
1
5
T
C
= 25°C
12
8
4
3 V
1.5
V
I
C
, COLLECTOR (AMP)
200
THERMAL LIMIT
BONDING WIRE LIMIT
SECOND BREAKDOWN LIM-
IT
CURVES APPLY BELOW RATED
V
CEO
The Safe Operating Area figures shown in Figures 1 and 2 are specified ratings for these devices under the test conditions shown.
Figure 3. Forward Bias Power Derating
T
C
, CASE TEMPERATURE (°C)
0
40 120 160
0.6
POWER DERATING FACTOR
SECOND BREAK-
DOWN DERATING
1
0.8
0.4
0.2
60 100 14080
THERMAL
DERATING
20
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 1 is based on T
C
= 25_C; T
J(pk)
is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when T
C
≥ 25_C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 1 may be found at
any case temperature by using the appropriate curve on
Figure 3.
T
J(pk)
may be calculated from the data in Figure 4. At high
case temperatures, thermal limitations will reduce the power
that can be handled to values less than the limitations
imposed by second breakdown. Use of reverse biased safe
operating area data (Figure 2) is discussed in the applications
information section.
t, TIME (ms)
1
0.01
0.01
0.7
0.2
0.1
0.05
0.02
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
0.05 1 2 5 10 20 50 100 200 500
Z
q
JC(t)
= r(t) R
q
JC
R
q
JC
= 1.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
Z
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
D = 0.5
0.02
SINGLE PULSE
0.1
0.1 0.50.2 1.0 k
0.5
0.3
0.07
0.03
0.02
Figure 4. Typical Thermal Response [Z
q
JC
(t)]
0.01
0.05
0.2
P1-P3P4-P6P7-P9P10-P10

MJE13009

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Manufacturer:
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Bipolar Transistors - BJT 12A 400V 100W NPN
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