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83054AGI-01LFT

P1-P3P4-P6P7-P9P10-P12P13-P14
83054I-01 Datasheet
©2015 Integrated Device Technology, Inc December 15, 20154
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V ± 5%, TA = -40°C TO 85°C
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
V
DD
= 3.3V ± 5% 2 V
DD
+ 0.3 V
V
DD
= 2.5V ± 5% 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage
V
DD
= 3.3V ± 5% -0.3 1.3 V
V
DD
= 2.5V ± 5% -0.3 0.7 V
I
IH
Input High Current
CLK0, CLK1,
SEL0:SEL3
V
DD
= 3.3V or 2.5V ± 5% 150 µA
OE V
DD
= 3.3V or 2.5V ± 5% 5 µA
I
IL
Input Low Current
CLK0, CLK1,
SEL0:SEL3
V
DD
= 3.3V or 2.5V ± 5% -5 µA
OE V
DD
= 3.3V or 2.5V ± 5% -150 µA
V
OH
Output HighVoltage; NOTE 1
V
DDO
= 3.3V ± 5% 2.6 V
V
DDO
= 2.5V ± 5% 1.8 V
V
DDO
= 1.8V ± 0.2V V
DD
- 0.3 V
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 3.3V ± 5% 0.5 V
V
DDO
= 2.5V ± 5% 0.45 V
V
DDO
= 1.8V ± 0.2V 0.35 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement section, “Load Test Circuit” diagrams.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High;
NOTE 1
1.8 2.5 3.2 ns
tp
HL
Propagation Delay, High to Low;
NOTE 1
2.0 2.6 3.2 ns
tsk(o) Output Skew; NOTE 2, 3 30 90 ps
tsk(i) Input Skew; NOTE 2 40 170 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
155.52, Integration Range:
12kHz – 20MHz
0.18 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 300 800 ps
odc Output Duty Cycle
ƒout ≤ 175MHz
40 60 %
MUX
ISOL
MUX Isolation @100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
83054I-01 Datasheet
©2015 Integrated Device Technology, Inc December 15, 20155
TABLE 5B. AC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, TA = -40°C TO 85°C
TABLE 5C. AC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High;
NOTE 1
2.1 2.6 3.1 ns
tp
HL
Propagation Delay, High to Low;
NOTE 1
2.3 2.7 3.1 ns
tsk(o) Output Skew; NOTE 2, 3 40 125 ps
tsk(i) Input Skew; NOTE 2 35 190 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
155.52, Integration Range:
12kHz – 20MHz
0.14 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 300 800 ps
odc Output Duty Cycle 40 60 %
MUX
ISOL
MUX Isolation @100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High;
NOTE 1
2.6 3.1 3.6 ns
tp
HL
Propagation Delay, High to Low;
NOTE 1
2.7 3.2 3.7 ns
tsk(o) Output Skew; NOTE 2, 3 40 125 ps
tsk(i) Input Skew; NOTE 2 35 195 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
155.52, Integration Range:
12kHz – 20MHz
0.16 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 450 850 ps
odc Output Duty Cycle 40 60 %
MUX
ISOL
MUX Isolation @100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
83054I-01 Datasheet
©2015 Integrated Device Technology, Inc December 15, 20156
TABLE 5D. AC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V ± 5%, TA = -40°C TO 85°C
TABLE 5E. AC CHARACTERISTICS, V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High;
NOTE 1
1.5 3.0 4.5 ns
tp
HL
Propagation Delay, High to Low;
NOTE 1
2.2 2.8 3.4 ns
tsk(o) Output Skew; NOTE 2, 3 30 90 ps
tsk(i) Input Skew; NOTE 2 45 190 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
155.52, Integration Range:
12kHz – 20MHz
0.22 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 300 700 ps
odc Output Duty Cycle
ƒout ≤175MHz
40 60 %
MUX
ISOL
MUX Isolation @100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High;
NOTE 1
2.2 3.2 4.2 ns
tp
HL
Propagation Delay, High to Low;
NOTE 1
2.5 3.2 4.0 ns
tsk(o) Output Skew; NOTE 2, 3 40 125 ps
tsk(i) Input Skew; NOTE 2 30 145 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
155.52, Integration Range:
12kHz – 20MHz
0.19 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 450 850 ps
odc Output Duty Cycle
ƒout ≤ 200MHz
40 60 %
MUX
ISOL
MUX Isolation @100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
P1-P3P4-P6P7-P9P10-P12P13-P14

83054AGI-01LFT

Mfr. #:
Buy 83054AGI-01LFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 4 bit 2:1 Single Ended MUX
Lifecycle:
New from this manufacturer.
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