Data Sheet ADP1822
Rev. D | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05311-005
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
19
18
17
16
15
14
13
12
11
NC = NO CONNECT
DH
SW
SYNC
TRKN
MAR
FREQ
BST
PVCC
DL
PGND
MUP
VCC
CSL
TRKP
SHDN
GND
DGND
PWGD
MDN
MSEL
SS
FB
COMP
NC
ADP1822
TOP VIEW
(Not to Scale)
Figure 4. ADP1822 Pin Configuration
Table 3. Pin Function Descriptions
1 BST
High-Side Gate Driver Boost Capacitor Input. A capacitor between SW and BST powers the high-side gate driver
DH. The capacitor is charged through a diode from PVCC when the low-side MOSFET is on. Connect a 0.1 µF or
greater ceramic capacitor from BST to SW and a Schottky diode from PVCC to BST to power the high-side gate
driver.
2 DH
High-Side Gate Driver Output. Connect DH to the gate of the external high-side N-channel MOSFET switch.
DH is powered from the capacitor between SW and BST and its voltage swings between V
SW
and V
BST
.
3 SW
Power Switch Node. SW is the power switching node. Connect the source of the high-side N-channel MOSFET
switch and the drain of the low-side N-channel MOSFET synchronous rectifier to SW. SW powers the output
through the output LC filter.
4 SYNC
Frequency Synchronization Input. Drive SYNC with an external 300 kHz to 1.2 MHz signal to synchronize the
converter switching frequency to the applied signal. The maximum SYNC frequency is limited to 2× the nominal
internal frequency selected by FREQ. Do not leave SYNC unconnected; when not used, connect SYNC to GND.
5 FREQ
Frequency Select Input. FREQ selects the converter switching frequency. Drive FREQ low to select 300 kHz, or
high to select 600 kHz. Do not leave FREQ unconnected.
6 MAR
Margin Control Input. MAR is used with MSEL to control output voltage margining. MAR chooses between
high voltage and low voltage margining when MSEL is driven high. If not used, connect MAR to GND.
7 TRKN
Tracking Comparator Negative Input. Drive TRKN from the voltage that the ADP1822 output voltage tracks.
TRKN voltage is limited to VCC. See the Output Voltage Tracking section.
8 TRKP
Tracking Comparator Positive Input. Drive TRKP from the output voltage. TRKP voltage is limited to VCC.
See the Output Voltage Tracking section.
9
SHDN Active Low DC-to-DC Shutdown Input. Drive SHDN high to turn on the converter. Drive it low to turn it off.
Connect SHDN to VCC for automatic startup.
10 PWGD
Open-Drain Power-Good Output. PWGD sinks current to GND when the output voltage is above or below
the regulation voltage. Connect a pull-up resistor from PWGD to VDD for a logical power-good indicator.
11 DGND Digital Ground. Connect DGND to GND at a single point as close as possible to the IC.
12 GND Analog Ground. Connect GND to PGND at a single point as close as possible to the IC.
13 SS
Soft Start Control Input. A capacitor from SS to GND controls the soft start period. When the output is overloaded,
SS is discharged to prevent excessive input current while the output recovers. Connect a 1 nF to 1 µF capacitor
from SS to GND to set the soft start period. See the Soft Start section.
14 FB
Voltage Feedback Input. Connect to a resistive voltage divider from the output to FB to set the output voltage.
See the Setting the Output Voltage section.
15 COMP
Compensation Node. Connect a resistor-capacitor network from COMP to FB to compensate the regulation
control system. See the Compensation section.
16 MSEL
Margin Select Input. Drive MSEL high to activate the voltage margining feature. Drive MSEL low to regulate
the output voltage to the nominal value. If not used, connect MSEL to GND.
