ZL30622 Product Brief
2
Microsemi Corporation
1. Application Examples
From line cards
and other clock
sources
19.44M,
25M, etc.
G.813/G.8262 compliance, input clock monitoring,
hitless switching, frequency conversion.
2x 156.25MHz differential
125MHz CMOS
25MHz CMOS
TCXO or
OCXO
Output jitter dependent on TCXO or OCXO jitter.
Holdover stability from TCXO or OCXO.
Figure 2 - Telecom Timing Card Application
2. Detailed Features
2.1 Input Block Features
Three input clocks, two differential or single-ended, one single-ended
Input clocks can be any frequency from 8kHz up to 1250MHz (differential) or 300MHz (single-ended)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the selected reference after a few missing clock cycles
Frequency measurement and monitoring with 1ppm resolution and accept/reject hysteresis
Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs
2.2 DPLL Features
Very high-resolution DPLL architecture
State machine automatically transitions between tracking and freerun/holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.1Hz to 500Hz
Less than 0.1dB gain peaking
Programmable phase-slope limiting
Programmable tracking range (i.e. hold-in range)
Truly hitless reference switching with <200ps output clock phase transient
Output phase adjustment in 10ps steps
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
Holdover frequency averaging with programmable averaging time and delay time
2.3 APLL Features
Very high-resolution fractional scaling (i.e. non-integer multiplication)
Any-to-any frequency conversion with 0ppm error
Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
Bypass mode supports system testing
2.4 Output Clock Features
Three low-jitter output clocks
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
Output jitter as low as 0.25ps RMS (12kHz to 20MHz)
In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
(Example 1: OC3P 125MHz, OC3N 25MHz. Example 2: OC2P 25MHz, OC2N 1Hz)
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
