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SIC639CD-T1-GE3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
SiC639
www.vishay.com
Vishay Siliconix
S18-0300-Rev. A, 19-Mar-18
10
Document Number: 76585
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
ELECTRICAL CHARACTERISTICS
Test condition: V
IN
= 13 V, DSBL# = V
DRV
= V
CIN
= 5 V, ZCD_EN# = 5 V, V
OUT
= 1 V, L
OUT
= 250 nH (DCR = 0.32 m), T
A
= 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated)
Fig. 18 - DSBL# Threshold vs. Temperature
Fig. 19 - DSBL# vs. Driver Input Voltage
Fig. 20 - DSBL# Pull-Down Current vs. Temperature
Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage
Fig. 22 - Driver Shutdown Current vs. Temperature
Fig. 23 - Driver Supply Current vs. Temperature
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
DSBL# Threshold Voltage, V
DSBL#
(V)
Driver Supply Voltage, V
CIN
(V)
V
IH_DSBL#
V
IL_DSBL#
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
ZCD_EN# Threshold Voltage, V
ZCD_EN#
(V)
Driver Supply Voltage, V
CIN
(V)
V
IH_ZCD_EN#_R
V
IL_ZCD_EN#_F
0
1
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Current, I
VDVR
& I
VCIN
(V)
Temperature (°C)
V
DSBL#
= 0 V
260
270
280
290
300
310
320
330
340
-60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Current, I
VDVR
& I
VCIN
(V)
Temperature (°C)
V
PWM
= FLOAT
SiC639
www.vishay.com
Vishay Siliconix
S18-0300-Rev. A, 19-Mar-18
11
Document Number: 76585
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PCB LAYOUT RECOMMENDATIONS
Step 1: V
IN
/GND Planes and Decoupling
1. Layout V
IN
and P
GND
planes as shown above
2. Ceramic capacitors should be placed right between V
IN
and P
GND
, and very close to the device for best
decoupling effect
3. Difference values / packages of ceramic capacitors
should be used to cover entire decoupling spectrum e.g.
1210, 0805, 0603 and 0402
4. Smaller capacitance value, closer to device V
IN
pin(s)
- better high frequency noise absorbing
Step 2: V
SWH
Plane
1. Connect output inductor to DrMOS with large plane to
lower the resistance
2. If any snubber network is required, place the
components as shown above and the network can be
placed at bottom
Step 3: V
CIN
/V
DRV
Input Filter
1. The V
CIN
/V
DRV
input filter ceramic cap should be placed
very close to IC. It is recommended to connect two caps
separately.
2. C
VCIN
cap should be placed between pin 3 and pin 4
(C
GND
of driver IC) to achieve best noise filtering.
3. C
VDRV
cap should be placed between pin 28 (P
GND
of
driver IC) and pin 29 to provide maximum instantaneous
driver current for low side MOSFET during switching
cycle
4. For connecting C
VCIN
analog ground, it is recommended
to use large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
1. These components need to be placed very close to IC,
right between PHASE (pin 7) and BOOT (pin 5).
2. To reduce parasitic inductance, chip size 0402 can be
used.
V
IN
V
SWH
P
GND
V
IN
plane
P
GND
plane
PGND Plane
VSWH
Snubber
V
SWH
P
GND
plane
C
GND
C
VCIN
C
VDRV
P
G
N
D
Cboot
Rboot
SiC639
www.vishay.com
Vishay Siliconix
S18-0300-Rev. A, 19-Mar-18
12
Document Number: 76585
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Step 5: Signal Routing
1. Route the PWM / ZCD_EN# / DSBL# / THWn signal
traces out of the top left corner next DrMOS pin 1.
2. PWM signal is very important signal, both signal and
return traces need to pay special attention of not letting
this trace cross any power nodes on any layer.
3. It is best to “shield” traces form power switching nodes,
e.g. V
SWH
, to improve signal integrity.
4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally.
Step 6: Adding Thermal Relief Vias
1. Thermal relief vias can be added on the V
IN
and P
GND
pads to utilize inner layers for high current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be put on V
IN
plane and P
GND
plane.
3. V
SWH
pad is a noise source and not recommended to put
vias on this plane.
4. 8 mil drill for pads and 10 mils drill for plane can be the
optional via size. Vias on pad may drain solder during
assembly and cause assembly issue. Please consult
with the assembly house for guideline.
Step 7: Ground Connection
1. It is recommended to make single connection between
C
GND
and P
GND
and this connection can be done on top
layer.
2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into C
GND
and P
GND
plane.
3. These ground planes provide shielding between noise
source on top layer and signal trace on bottom layer.
P
GND
C
GND
C
GND
V
IN
plane
P
GND
plane
V
SWH
P
GND
V
IN
C
GND
V
SWH
P
GND
C
GND
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

SIC639CD-T1-GE3

Mfr. #:
Buy SIC639CD-T1-GE3
Manufacturer:
Vishay / Siliconix
Description:
Power Management Specialized - PMIC 50A 1.5MHz 19V PowerPAK MLP55-31L
Lifecycle:
New from this manufacturer.
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