AD5220
–7–REV. 0
V+
DUT
V
MS
A
B
W
V+ = V
DD
1LSB = V+/128
Figure 27. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
I
W
DUT
V
MS
A
B
W
Figure 28. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
V
MS2
V
W
I
W
=
V
DD
/R
NOMINAL
DUT
V
MS1
A
B
W
R
W
= [V
MS1
– V
MS2
]/I
W
␣ ␣ Figure 29.␣ Wiper Resistance Test Circuit
PSRR (dB) = 20 LOG
(
–––––
)
PSS (%/%) = –––––––
DV
MS
DV
DD
DV
MS
%
DV
DD
%
V+ = V
DD
± 10%
V
DD
V
A
~
V+
V
MS
A
B
W
Figure 30. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
~
A
B
V
IN
2.5V DC
OP279
+5V
V
OUT
DUT
W
OFFSET
GND
Figure 31. Inverting Programmable Gain Test Circuit
~
AB
V
IN
2.5V
OP279
+5V
V
OUT
DUT
W
OFFSET
GND
Figure 32. Noninverting Programmable Gain Test Circuit
A
B
2.5V
DUT
W
OFFSET
GND
~
V
IN
OP42
+15V
V
OUT
–15V
Figure 33. Gain vs. Frequency Test Circuit
I
SW
0 TO V
DD
R
SW
=
0.1V
I
SW
CODE = ØØ
H
0.1V
DUT
B
W
Figure 34. Incremental ON Resistance Test Circuit
Parametric Test Circuits–
AD5220
–8–
REV. 0
OPERATION
The AD5220 provides a 128-position digitally controlled vari-
able resistor (VR) device. Changing the VR settings is accom-
plished by pulsing the CLK pin while CS is active low. The
direction of the increment is controlled by the U/D (UP/DOWN)
control input pin. When the wiper hits the end of the resistor
(Terminals A or B) additional CLK pulses no longer change
the wiper setting. The wiper position is immediately decoded
by the wiper decode logic changing the wiper resistance. Ap-
propriate debounce circuitry is required when push button
switches are used to control the count sequence and direction
of count. The exact timing requirements are shown in Figure 3.
The AD5220 powers ON in a centered wiper position exhibit-
ing nearly equal resistances of R
WA
and R
WB
.
UP/
DOWN
CNTR
RS
D
E
C
O
D
E
7
40
H
POR
EN
AD5220
V
DD
A
W
B
GND
CLK
CS
U/D
Figure 35. Block Diagram
DIGITAL INTERFACING OPERATION
The AD5220 contains a three-wire serial input interface. The
three inputs are clock (CLK), CS and UP/DOWN (U/D). The
negative-edge sensitive CLK input requires clean transitions to
avoid clocking multiple pulses into the internal UP/DOWN
counter register, see Figure 35. Standard logic families work
well. If mechanical switches are used for product evaluation
they should be debounced by a flip-flop or other suitable
means. When CS is taken active low the clock begins to incre-
ment or decrement the internal UP/DOWN counter dependent
upon the state of the U/D control pin. The UP/DOWN counter
value (D) starts at 40
H
at system power ON. Each new CLK
pulse will increment the value of the internal counter by one
LSB until the full scale value of 3F
H
is reached as long as the
U/D pin is logic high. If the U/D pin is taken to logic low the
counter will count down stopping at code 00
H
(zero-scale).
Additional clock pulses on the CLK pin are ignored when the
wiper is at either the 00
H
position or the 3F
H
position.
All digital inputs (CS, U/D, CLK) are protected with a series
input resistor and parallel Zener ESD structure shown in
Figure 36.
LOGIC
1kV
Figure 36. Equivalent ESD Protection Digital Pins
20V
A, B, W
GND
Figure 37. Equivalent ESD Protection Analog Pins
D0
D1
D2
D3
D4
D5
D6
RDAC
UP/DOWN
CNTR
&
DECODE
Wx
Bx
R
S
= R
NOMINAL
/128
R
S
R
S
R
S
Ax
Figure 38. AD5220 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available with values of 10 k, 50 k, and 100 k. The
final three characters of the part number determine the nominal
resistance value, e.g., 10 k =10; 50 k = 50; 100 k = 100.
The nominal resistance (R
AB
) of the VR has 128 contact points
accessed by the wiper terminal, plus the B terminal contact. At
power ON the resistance from the wiper to either end Terminal
A or B is approximately equal. Clocking the CLK pin will in-
crease the resistance from the Wiper W to Terminal B by one
unit of R
S
resistance (see Figure 38). The resistance R
WB
is
determined by the number of pulses applied to the clock pin.
Each segment of the internal resistor string has a nominal resis-
tance value of R
S
= R
AB
/128, which becomes 78 in the case of
the 10 k AD5220BN10 product. Care should be taken to limit
the current flow between W and B in the direct contact state to
a maximum value of 5 mA to avoid degradation or possible de-
struction of the internal switch contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical (see Figure 38). The resistance between the
Wiper W and Terminal A also produces a digitally controlled
resistance R
WA
. When these terminals are used the B–terminal
should be tied to the wiper.
The typical part-to-part distribution of R
BA
is process lot depen-
dent having a ±30% variation. The change in R
BA
with tempera-
ture has a 800 ppm/°C temperature coefficient.
The R
BA
temperature coefficient increases as the wiper is pro-
grammed near the B-terminal due to the larger percentage con-
tribution of the wiper contact switch resistance, which has a
0.5%/°C temperature coefficient. Figure 14 shows the effect of
the wiper contact resistance as a function of code setting. An-
other performance factor influenced by the switch contact resis-
tance is the relative linearity error performance between the
10 k, and the 50 k or 100 k versions. The same switch
contact resistance is used in all three versions. Thus the perfor-
mance of the 50 k and 100 k devices which have the least
impact on wiper switch resistance exhibits the best linearity
error, see Figures 7 and 8.
AD5220
–9–REV. 0
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A Terminal to +5 V and B Terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminals
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is:
V
W
(D) = D/128 × V
AB
+ V
B
(1)
D represents the current contents of the internal UP/DOWN
counter.
Operation of the digital potentiometer in the divider mode re-
sults in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value, therefore, the drift improves to 20 ppm/°C.
APPLICATIONS INFORMATION
The negative-edge sensitive CLK pin does not contain any
internal debounce circuitry. This standard CMOS logic input
responds to fast negative edges and needs to be debounced
externally with an appropriate circuit designed for the type of
switch closure device being used. Good performance results at
the CLK input pin when the negative logic transition has a
minimum slew rate of 1 V/µs. A wide variety of standard circuits
can be used such as a one-shot multivibrator, Schmitt Triggered
gates, cross coupled flip-flops, or RC filters to drive the CLK
pin with uniform negative edges. This will prevent the digital
potentiometer from skipping output codes while counting due to
switch contact bounce.

604-00010

Mfr. #:
Manufacturer:
Parallax
Description:
Digital Potentiometer ICs 10k Digital Porentiometer
Lifecycle:
New from this manufacturer.
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