10©2016 Integrated Device Technology, Inc Revision A January 15, 2016
840001I-34 Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the
footprint of the package corresponding to the exposed metal pad
or exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask,
should be at least the same size/shape as the exposed pad/slug
area on the package to maximize the thermal/electrical
performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges
of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering
process which may result in voids in solder between the exposed
pad/slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the
Application Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
11©2016 Integrated Device Technology, Inc Revision A January 15, 2016
840001I-34 Data Sheet
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 16 Lead VFQFN
Transistor Count
The transistor count for 840001I-34 is: 2805
JA
at 0 Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 76.1°C/W 66.5 59.7
12©2016 Integrated Device Technology, Inc Revision A January 15, 2016
840001I-34 Data Sheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol Minimum Maximum
N 16
A 0.80 1.00
A1 00.05
A3 0.25 Ref.
b 0.18 0.30
N
D
& N
E
4
D & E 3.00 Basic
D2 & E2 1.00 1.80
e 0.50 Basic
L 0.30 0.50
Top View
Index
A
rea
D
Cham fer 4x
0.6 x 0.6 max
OPTIONAL
A
0. 08 C
C
A3
A1
Seating Plan
e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Eve
n
N
e
D2
2
D2
(Ref.)
N& N
Od
d
1
2
e
2
(Typ.)
If N & N
are Eve
n
(N -1)x e
(Re f.)
b
Thermal
Bas
e
N
DE
D
DE
DE
E
Anvil
Singulation
or
Sawn
Singulation

840001AKI-34LFT

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 2 LVCMOS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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