7
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32866B
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FUNCTION TABLE (EACH FLIP-FLOP)
(1)
Inputs Qx QCSx QODTx, QCKEx
RESET DCS CSR CLK CLK Dx, DODT, DCKE Outputs Output Outputs
HLL ↑↓ LLLL
HLL ↑↓ HHLH
H L L L or H L or H X Q
0
(2)
Q
0
(2)
Q
0
(2)
HLH ↑↓ LLLL
HLH ↑↓ HHLH
H L H L or H L or H X Q
0
(2)
Q
0
(2)
Q
0
(2)
HHL ↑↓ LLHL
HHL ↑↓ HHHH
H H L L or H L or H X Q
0
(2)
Q
0
(2)
Q
0
(2)
HHH ↑↓ LQ
0
(2)
HL
HHH ↑↓ HQ
0
(2)
HH
H H H L or H L or H X Q
0
(2)
Q
0
(2)
Q
0
(2)
L X or Floating X or Floating X or Floating X or Floating X or Floating L L L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Output level before the indicated steady-state conditions were established.
PARITY AND STANDBY FUNCTION TABLE
(1)
Inputs Outputs
RESET DCS CSR CLK CLK
ΣΣ
ΣΣ
Σ of Inputs = H (D1 - D25) PAR_IN
(2)
PPO
(3)
QERR
(4)
HLX↑↓ Even L L H
HLX↑↓ Odd L H L
HLX↑↓ Even H H L
HLX↑↓ Odd H L H
HHL ↑↓ Even L L H
HHL ↑↓ Odd L H L
HHL ↑↓ Even H H L
HHL ↑↓ Odd H L H
HHH ↑↓ X X PPO
0
QERR
0
H X X L or H L or H X X PPO
0
QERR
0
L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating L H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
3. PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
4. This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET
is driven LOW.
