December 1990 2
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
FEATURES
• Simultaneous and independent read and write
operations
• Expandable to almost any word size and bit length
• Output capability: bus driver
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
organized as 4 words of 4 bits each. Separated read and
write address inputs (R
A
, R
B
and W
A
,W
B
) and enable
inputs (RE and WE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D
0
to D
3
). The W
A
and W
B
inputs determine
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q
0
to Q
3
). D
n
and W
n
inputs are inhibited when
WE is HIGH.
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(R
A
and R
B
). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
;
for HCT the condition is V
I
= GND to V
CC
−1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay D
n
to Q
n
C
L
= 15 pF; V
CC
= 5 V 23 23 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 122 124 pF
