December 1990 8
Philips Semiconductors Product specification
4 x 4 register file; 3-state 74HC/HCT670
AC WAVEFORMS
Fig.6 Waveforms showing the read address input
(R
A
, R
B
) to output (Q
n
) propagation delays
and output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7 Waveforms showing the write enable input
(WE) and data input (D
n
) to output (Q
n
)
propagation delays, and the write enable
pulse width.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.8 Waveforms showing the write address input (W
A
, W
B
) and data input (D
n
) to write enable (WE) set-up,
hold and latch times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
The time allowed for the internal output of the latch to
assume the state of the new data (t
latch
) is important
only when attempting to read from a location
immediately after that location has received new data.
This parameter is measured from the falling edge of
WE to the rising edge of R
A
or R
B
, RE must be LOW.
