DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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7
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Selector Guide
PART
FREQUENCY
(NOM) (MHz)
OUTPUT
TYPE
TOP MARK
DS4M125P+33 125 LVPECL MEP
DS4M125D+33 125 LVDS MED
DS4M133P+33 133.33 LVPECL MFP
DS4M133D+33 133.33 LVDS MFD
DS4M200P+33 200 LVPECL MJP
DS4M200D+33 200 LVDS MJD
+
Denotes a lead-free package. The lead finish is JESD97 cate-
gory e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes. A + appears anywhere on
the top mark.
Chip Information
SUBSTRATE CONNECTED TO GROUND
PROCESS: BiPOLAR SiGe
THETA-JA (°C/W)
90
1
2
3
6
5
4
TOP VIEW
OE
MS
N.C. N.C.
N.C. N.C.
GND
VCC
OUTN
OUTP
+
(5.00mm
3.20mm
1.49mm)
DS4M125/
DS4M133/
DS4M200
*EP
*EXPOSED PAD
Pin Configuration
Thermal Information
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 LCCC L1053+H2
21-0389
