74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 24 April 2008 3 of 18
NXP Semiconductors
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aac423
3
1
2
4
5
6
10
11
12
13
8
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
DSB
DSA
MR
001aac424
9
8
&
3
1
2
4
5
6
10
11
13
12
R
C1/
1D
SRG8
Fig 4. Logic diagram
001aac616
Q0
D
FF1
Q
CP
R
D
CP
DSB
DSA
MR
Q1
D
FF2
Q
CP
R
D
Q2
D
FF3
Q
CP
R
D
Q3
D
FF4
Q
CP
R
D
Q4
D
FF5
Q
CP
R
D
Q5
D
FF6
Q
CP
R
D
Q6
D
FF7
Q
CP
R
D
Q7
D
FF8
Q
CP
R
D
74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 24 April 2008 4 of 18
NXP Semiconductors
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14
164
DSA V
CC
DSB Q7
Q0 Q6
Q1 Q5
Q2 Q4
Q3 MR
GND
CP
001aac422
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aac828
164
GND
(1)
Transparent top view
Q3 MR
Q2 Q4
Q1 Q5
Q0 Q6
DSB Q7
GND
CP
DSA
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
DSA 1 serial data input A
DSB 2 serial data input B
Q0 3 output 0
Q1 4 output 1
Q2 5 output 2
Q3 6 output 3
GND 7 ground (0 V)
CP 8 clock input (LOW-to-HIGH edge-triggered)
MR 9 master reset input (active LOW)
Q4 10 output 4
Q5 11 output 5
Q6 12 output 6
Q7 13 output 7
V
CC
14 supply voltage
74AHC_AHCT164_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 24 April 2008 5 of 18
NXP Semiconductors
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH transition;
X = don’t care;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of P
tot
derates linearly at 4.5 mW/K.
Table 3. Function table
[1]
Operating mode Control Input Output
MR CP DSA DSB Q0 Q1 to Q7
Reset (clear) L X X X L L to L
Shift H l l L q0 to q6
l h L q0 to q6
h l L q0 to q6
h h H q0 to q6
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
V
I
input voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V
[1]
20 - mA
I
OK
output clamping current V
O
< 0.5 V or V
O
> V
CC
+ 0.5 V
[1]
20 +20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) 25 +25 mA
I
CC
supply current - +75 mA
I
GND
ground current 75 - mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
[2]
- 500 mW

74AHCT164PW,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 8-BIT SI-PO SHIFT
Lifecycle:
New from this manufacturer.
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