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PI4IOE5V9537UEX

P1-P3P4-P6P7-P9P10-P12P13-P13
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2016-01-0029 PT0565-1 02/15/16
4
PI4IOE5V9537
4-bit I
2
C-bus and SMBus
low power I/O port with interrupt and reset
Parameter
Conditions
Min.
Typ.
Max.
Unit
I/Os
Low level input voltage
-0.5
-
+0.81
V
High level input voltage
+1.8
-
5.5
V
Low level output current
VCC = 2.3 V; V
OL
= 0.5 V
[2]
8
10
-
mA
VCC
= 2.3 V; V
OL
= 0.7 V
[2]
10
13
-
mA
VCC = 3.0 V; V
OL
= 0.5 V
[2]
8
14
-
mA
VCC
= 3.0 V; V
OL
= 0.7 V
[2]
10
19
-
mA
VCC = 4.5 V; V
OL
= 0.5 V
[2]
8
17
-
mA
VCC
=4.5 V; V
OL
= 0.7 V
[2]
10
24
-
mA
High level output voltage
I
OH
=-8mA;VCC=2.3V
[3]
1.8
-
-
V
I
OH
=-10mA;VCC=2.3V
[3]
1.7
-
-
V
I
OH
=-8mA;VCC=3.0V
[3]
2.6
-
-
V
I
OH
=-10mA;VCC=3.0V
[3]
2.5
-
-
V
I
OH
=-8mA;VCC=4.75V
[3]
4.1
-
-
V
I
OH
=-10mA;VCC=4.75V
[3]
4.0
-
-
V
input leakage current
VCC=3.6V; V
I
=VCC=GND
-1
-
1
μA
Input capacitance
-
3.7
10
pF
Interrupt
INT
Low level output current
V
OL
=0.4V
3
13
-
mA
High level output current
V
OL
=0.4V
-1
+1
uA
Select inputs A0,A1 and
RESET
Low level input voltage
-0.5
-
+0.81
V
High level input voltage
+1.8
-
5.5
V
Input leakage current
V
I
=VCC=GND
-1
1
μA
Note:
[1]: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
[2]: Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3]: The total current sourced by all I/Os must be limited to 85 mA.
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2016-01-0029 PT0565-1 02/15/16
5
PI4IOE5V9537
4-bit I
2
C-bus and SMBus
low power I/O port with interrupt and reset
Dynamic Characteristics
Table 3: Dynamic characteristics
Symbol
Parameter
Test
Conditions
Standard
mode I
2
C
Fast mode
I
2
C
Fast mode
Plus I
2
C
Unit
Min
Max
Min
Max
Min
Max
f
SCL
SCL clock frequency
0
100
0
400
0
1000
kHz
t
BUF
bus free time between a STOP
and START condition
4.7
-
1.3
-
0.5
-
μs
t
HD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
μs
t
SU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
μs
t
SU;STO
set-up time for STOP condition
4.0
-
0.6
-
0.26
-
μs
t
VD;ACK
[1]
data valid acknowledge time
-
3.45
-
0.9
-
0.45
μs
t
HD;DAT
[2]
data hold time
0
-
0
-
0
-
ns
t
VD;DAT
data valid time
-
3.45
-
0.9
-
0.45
us
t
SU;DAT
data set-up time
250
-
100
-
50
-
ns
t
LOW
LOW period of the SCL clock
4.7
-
1.3
-
0.5
-
μs
t
HIGH
HIGH period of the SCL clock
4.0
-
0.6
-
0.26
-
μs
t
f
fall time of both SDA and SCL
signals
-
300
-
300
-
120
ns
t
r
rise time of both SDA and SCL
signals
-
1000
-
300
-
120
ns
t
SP
pulse width of spikes that must
be
suppressed by the input filter
-
50
-
50
50
ns
Port timing
t
v(Q)
Data output valid time
[3]
-
200
-
200
-
200
ns
t
su(D)
Data input set-up time
100
-
100
-
100
-
ns
t
h(D)
Data input hold time
1
-
1
-
1
-
μs
Interrupt timing
t
v(INT)
Valid time on pin
INT
-
4
-
4
-
4
μs
t
rst(INT)
Reset time on pin
INT
-
4
-
4
-
4
μs
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2016-01-0029 PT0565-1 02/15/16
6
PI4IOE5V9537
4-bit I
2
C-bus and SMBus
low power I/O port with interrupt and reset
Symbol
Parameter
Test
Conditions
Standard
mode I
2
C
Fast mode
I
2
C
Fast mode
Plus I
2
C
Uint
Min
Max
Min
Max
Min
Max
RESET
timing
t
w(rst)
Reset pulse width
25
-
25
-
25
-
ns
t
vrec(rst)
Reset recovery time
[4]
0
-
0
-
0
-
ns
t
rst
Reset time
1
-
1
-
1
-
us
Note:
[1]: t
VD;ACK
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3]: t
v(Q)
measured from 0.7VCC on SCL to 50% I/O output.
[4]: To reset the device while actively communicating on the bus may cause glitches or errant STOP conditions. Upon reset, the
full delay will be the sum of t
rst
and RC time constant of SDA bus.
Figure 2: timing parameters for INT signal
P1-P3P4-P6P7-P9P10-P12P13-P13

PI4IOE5V9537UEX

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Description:
4-Bit I2C-Bus And Smbus Low Power I/O Port With Interrupt And Reset
Lifecycle:
New from this manufacturer.
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