AD5441
Rev. A | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= 5 V, V
REF
= 10 V, −40°C < T
A
< +155°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Condition
STATIC PERFORMANCE
Resolution N 12 Bits
Relative Accuracy INL ±0.5 LSB
Differential Nonlinearity DNL ±0.5 LSB All grades monotonic to 12 bits
Gain Error G
FSE
±1 LSB Data = FFF
H
Gain Temperature Coefficient
1
TCG
FS
±5 ppm/°C I
OUT
pin measured
Output Leakage Current I
LKG
±5 nA Data = 000
H
, I
OUT
pin measured
±25 nA T
A
= –40°C, +125°C, data = 000
H
, I
OUT
pin measured
Zero-Scale Error I
ZSE
±0.03 LSB Data = 000
H
±0.15 LSB T
A
= −40°C, +125°C, data = 000
H
REFERENCE INPUT
Input Resistance R
REF
7 15 Absolute temperature coefficient < 50 ppm/°C
Input Capacitance
1
C
REF
5 pF
ANALOG OUTPUT
Output Capacitance
1
C
OUT
1 pF Data = 000
H
4 pF Data = FFF
H
DIGITAL INPUTS
Digital Input Low V
IL
0.8 V
Digital Input High V
IH
2.4 V
Input Leakage Current I
IL
1 μA V
LOGIC
= 0 V to 5 V
Input Capacitance
1
C
IL
4.0 pF V
LOGIC
= 0 V
AC CHARACTERISTICS
1
Output Current Settling Time t
S
5 μs To ±0.01% of full-scale, external op amp OP42
0.5 μs To ±0.01% of full-scale, 100 Ω terminated to ground
DAC Glitch Q 40 nVs Data = 000
H
to FFF
H
to 000
H
, V
REF
= 0 V, OP42
1 nVs Data = 000
H
to FFF
H
to 000
H
, V
REF
= 0 V, 100 Ω
Digital Feedthrough 5 nV Using external op amp OP42
Feedthrough (V
OUT
/V
REF
) FT 1.4 mV p-p V
REF
= 20 V p-p, data = 000
H
, f = 10 kHz
Total Harmonic Distortion THD −85 dB V
REF
= 6 V rms, data = FFF
H
, f = 1 kHz
Output Noise Density e
n
17 nV/√Hz 10 Hz to 100 kHz between R
FB
and I
OUT
Multiplying Bandwidth BW 1.9 MHz −3 dB, V
OUT
/V
REF
, V
REF
= 100 mV rms, data = FFF
H
SUPPLY CHARACTERISTICS
1
Power Supply Range V
DD RANGE
2.5 5.5 V
Positive Supply Current I
DD
10 μA V
LOGIC
= 0 V or V
DD
Power Dissipation P
DISS
2.5 5.5 μW V
LOGIC
= 0 V or V
DD
Power Supply Sensitivity PSS 0.002 %/% ΔV
DD
= ±5%
1
These parameters are guaranteed by design and not subject to production testing.
AD5441
Rev. A | Page 4 of 16
TIMING CHARACTERISTICS
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2; V
DD
+ 2.5 V
to 5.5 V, V
REF
= 10 V; temperature range = −40°C to +125°C; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. Timing Characteristics
Parameter 2.5 V 5.5 V Unit Conditions/Comments
t
DS
10 5 ns min Data setup
t
DH
5 5 ns min Data hold
t
CH
15 10 ns min Clock width high
t
CL
15 10 ns min Clock width low
t
LD
20 10 ns min Load pulse width
t
LD1
0 0 ns min
LD
DAC high to MSB CLK high
t
ASB
0 0 ns min
LSB CLK to LD
DAC
Timing Diagrams
SRI
CLK
LD
D11
D10D9D8 D6D5D4D3D2D1D0D7
t
LD1
t
ASB
DAC REGISTER LOAD
0
6492-102
Figure 2. Full Data Transmission
SRI
CLK
t
DS
t
DH
t
CL
t
CH
Dxx
DATA LOADED MSB(D11) FIRST
0
6492-103
Figure 3. Bit Data Transmission
FS
ZS
V
OUT
t
LD
±1LSB
ERROR BAND
LD
06492-104
Figure 4. Output Transition
Table 3. Control Logic Truth Table
CLK
LD
Serial Shift Register Function DAC Register Function
1
H Shift register data advanced one bit Latched
L Shift register data advanced one bit Transparent
H or L L No effect Updated with current shift register contents
L
1
No effect Latched all 12 bits
1
equals positive logic transition.
AD5441
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
V
DD
to GND −0.3 V, +8 V
V
REF
to GND ±18 V
R
FB
to GND ±18 V
Logic Inputs to GND −0.3 V, V
DD
+ 0.3 V
I
OUT
to GND −0.3 V, V
DD
+ 0.3 V
I
OUT
Short Circuit to GND 50 mA
Package Power Dissipation (T
J
max − T
A
)/θ
JA
Maximum Junction Temperature (T
J
max) 150°C
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5.
Package Type θ
JA
θ
JC
Unit
8-Lead MSOP 142 44 °C/W
8-Lead LFCSP
1
75 18 °C/W
1
Exposed pad soldered to the ground plane.
ESD CAUTION

AD5441BCPZ-REEL7

Mfr. #:
Manufacturer:
Description:
Digital to Analog Converters - DAC 12-Bit Serial Input Multiplying
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