Data Sheet ADuM5020/ADuM5028
Rev. 0 | Page 15 of 18
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM5020 and ADuM5028 isoPower integrated dc-to-dc
converters require
power supply bypassing at the input and
output supply pins (see Figure 25 and Figure 26). Low effective
series resistance (ESR) 0.1 μF bypass capacitors are required
between the V
DDP
pin and GND
1
pin, as close to the chip pads
as possible. Low ESR 0.1 μF or 0.22 μF capacitors are required
between the V
ISO
pin and GND
ISO
pin, as close to the chip pads
as possible (see the C
ISO
note in Figure 23 and Figure 24 for
more information). The isoPower inputs require multiple
passive components to bypass the power effectively, as well as
set the output voltage and bypass the core voltage regulator (see
Figure 21 through Figure 26).
PDIS
V
DDP
GND
1
GND
1
10µF
0.1µF
4
3
5
6
16520-018
Fig
ure 21. ADuM5020 V
DDP
Bias and Bypass Components
PDIS
V
DDP
GND
1
GND
1
10µF
0.1µF
2
1
3
4
16520-122
Fig
ure 22. ADuM5028 V
DDP
Bias and Bypass Components
GND
ISO
VISO OUT
FB2
GND
ISO
V
ISO
C
ISO
10µF
13
V
SEL
14
12
11
FB1
16520-019
C
ISO
= 0.1µF FOR V
DDP
= 5V AND V
ISO
= 5V,
C
ISO
= 0.22µF FOR V
DDP
= 5V AND V
ISO
= 3.3V
Fig
ure 23. ADuM5020 V
ISO
Bias and Bypass Components
GND
ISO
VISO OUT
FB2
GND
ISO
V
ISO
C
ISO
10µF
7
V
SEL
8
6
5
FB1
16520-124
C
ISO
= 0.1µF FOR V
DDP
= 5V AND V
ISO
= 5V,
C
ISO
= 0.22µF FOR V
DDP
= 5V AND V
ISO
= 3.3V
Fig
ure 24. ADuM5028 V
ISO
Bias and Bypass Components
The power supply section of the ADuM5020 and ADuM5028
uses a 180 MHz oscillator frequency to efficiently pass power
through its chip scale transformers. Bypass capacitors are required
for several operating frequencies. Noise suppression requires a
low inductance, high frequency capacitor, whereas ripple
suppression and proper regulation require a large value capacitor.
These capacitors are most conveniently connected between the
V
DDP
pin and GND
1
pin, and between the V
ISO
pin and GND
ISO
pin.
To suppress noise and reduce ripple, a parallel combination of at
least two capacitors is required. The recommended capacitor values
are 0.1 μF and 10 μF for V
DDP
and V
ISO
. The smaller capacitor
must have a low ESR. For example, use of a ceramic capacitor is
advised. The total lead length between the ends of the 0.1 μF low
ESR capacitors, and the power supply pins must not exceed 2 mm.
To reduce the level of electromagnetic radiation, the impedance
to high frequency currents between the V
ISO
and GND
ISO
pins and
the PCB trace connections can be increased. Using this method
of electromagnetic interference (EMI) suppression controls the
radiating signal at its source by placing surface-mount ferrite beads
in series with the V
ISO
and GND
ISO
pins, as shown in Figure 25
and Figure 26. The impedance of the ferrite bead is chosen to be
about 1.8 kΩ between the 100 MHz and 1 GHz frequency range to
reduce the emissions at the 180 MHz primary switching frequency
and the 360 MHz secondary side rectifying frequency and
harmonics. See Table 18 for examples of appropriate surface-
mount ferrite beads.
Table 18. Surface-Mount Ferrite Beads Example
Manufacturer Part No.
Taiyo Yuden BKH1005LM182-T
Murata Electronics BLM15HD182SN1
16520-020
C
ISO
0.1µF10µF
FERRITES
10µF
DuM5020
BYPASS <2mm
GND
ISO
V
DDP
GND
1
GND
1
GND
1
PDIS
NIC
NIC
GND
1
NIC
NIC
GND
ISO
GND
ISO
V
SEL
V
ISO
GND
ISO
V
ISO
OUT
C
ISO
= 0.1µF FOR V
DDP
= 5V AND V
ISO
= 5V,
C
ISO
= 0.22µF FOR V
DDP
= 5V AND V
ISO
= 3.3V
Fi
gure 25. Recommended ADuM5020 PCB Layout
16520-126
C
ISO
0.1µF10µF
FERRITES
10µF
DuM5028
BYPASS <2mm
GND
ISO
V
DDP
GND
1
GND
1
PDIS
GND
ISO
V
SEL
V
ISO
ISO OU
C
ISO
= 0.1µF FOR V
DDP
= 5V AND V
ISO
= 5V,
C
ISO
= 0.22µF FOR V
DDP
= 5V AND V
ISO
= 3.3V
Figure 26. Recommended ADuM5028 PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
