LTC6605-14
4
660514f
AC ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
+
= 3V, V
–
= 0V, V
INCM
= V
OCM
= mid-supply, V
BIAS
= V
+
, unless
otherwise noted. Filter confi gured as in Figure 2, unless otherwise noted. V
S
is defi ned as (V
+
– V
–
). V
OUTCM
is defi ned as (V
+OUT
+
V
–OUT
)/2. V
INCM
is defi ned as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defi ned as (V
+OUT
– V
–OUT
). V
INDIFF
is defi ned as (V
+IN
+ V
–IN
).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the LTC6605-14’s supply voltage, the excess input
current (current in excess of what it takes to drive that pin to the supply
rail) should be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefi nitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4: Both the LTC6605C and the LTC6605I are guaranteed functional
over the operating temperature range –40°C to 85°C.
Note 5: The LTC6605C is guaranteed to meet specifi ed performance
from 0°C to 70°C. The LTC6605C is designed, characterized and
expected to meet specifi ed performance from –40°C to 85°C, but is
not tested or QA sampled at these temperatures. The LTC6605I is
guaranteed to meet specifi ed performance from –40°C to 85°C.
Note 6: Output referred voltage offset is a function of gain. To determine
output referred voltage offset, or output voltage offset drift, multiply V
OS
by the noise gain (1 + GAIN). See Figure 3.
Note 7: Input bias current is defi ned as the average of the currents
fl owing into the noninverting and inverting inputs of the internal amplifi er
and is calculated from measurements made at the pins of the IC. Input
offset current is defi ned as the difference of the currents fl owing into
the noninverting and inverting inputs of the internal amplifi er and is
calculated from measurements made at the pins of the IC.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gain Filter Gain ΔV
IN
= ±0.125V, DC
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
V
INDIFF
= 0.5V
P-P
, f = 28MHz
V
INDIFF
= 0.5V
P-P
, f = 70MHz
l
l
l
l
l
l
–0.25
–1.25
–2.5
–4.15
–11.65
–28
±0.05
–0.92
–2.12
–3.75
–11.1
–25.2
0.25
–0.6
–1.75
–3.35
–10.6
–24.3
dB
dB
dB
dB
dB
dB
Phase Filter Phase ΔV
IN
= ±0.125V, DC
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
0
–43.3
–63.6
–81.2
Deg
Deg
Deg
Deg
ΔGain Gain Match (Channel-to-Channel) ΔV
IN
= ±0.125V, DC
V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
l
l
l
l
–0.175
–0.2
–0.2
–0.25
±0.04
±0.04
±0.04
±0.05
0.175
0.2
0.2
0.25
dB
dB
dB
dB
ΔPhase Phase Match (Channel-to-Channel) V
INDIFF
= 0.5V
P-P
, f = 7MHz
V
INDIFF
= 0.5V
P-P
, f = 10.5MHz
V
INDIFF
= 0.5V
P-P
, f = 14MHz
l
l
l
–0.9
–1.0
–1.1
±0.2
±0.2
±0.2
0.9
1.0
1.1
Deg
Deg
Deg
2V/V Gain Filter Gain in 2V/V Confi guration
Inputs at ±IN1 Pins, ±IN2 Pins Floating
ΔV
IN
= ±0.125V, DC
l
5.8 6 6.25 dB
Channel Separation V
INDIFF
= 1V
P-P
, f = 7MHz –96 dB
f
O
TC Filter Cut-Off Frequency Temperature
Coeffi cient (T = –45°C to 85°C)
BIAS = V
+
BIAS = Floating
–95
–230
ppm/°C
ppm/°C
Noise Integrated Output Noise
(BW = 10kHz to 28MHz)
54 μV
RMS
Input Referred Noise Density
(f = 1MHz)
BIAS = V
+
Figure 4, Gain = 1
Figure 4, Gain = 2
Figure 4, Gain = 3
13.2
6.6
4.4
nV/√Hz
nV/√Hz
nV/√Hz
e
n
Voltage Noise Density Referred to
Op Amp Inputs (f = 1MHz)
BIAS = V
+
BIAS = Floating
2.1
2.6
nV/√Hz
nV/√Hz
i
n
Current Noise Density Referred to
Op Amp Inputs (f = 1MHz)
BIAS = V
+
BIAS = Floating
3
2.1
pA/√Hz
pA/√Hz
HD2 2nd Harmonic Distortion
f
IN
= 7MHz; V
IN
= 2V
P-P
Single-Ended
BIAS = V
+
BIAS = Floating, R
LOAD
= 400Ω
–81
–69
dBc
dBc
HD3 3rd Harmonic Distortion
f
IN
= 7MHz; V
IN
= 2V
P-P
Single-Ended
BIAS = V
+
BIAS = Floating, R
LOAD
= 400Ω
–93
–76
dBc
dBc
