ISL6558IRZ-TK Datasheet ISL6558CBZA, ISL6558IRZ-T, ISL6558CRZ-T | P10-P12

FN9027.13

August 28, 2015

The PWM drive signals are switched out of phase. The PWM

drive signal phase relationship is 360° divided by the number

of active channels. Figure shows the PWM drive signals for

a four channel converter running at 125kHz. Each PWM

drive signal is 90° out of phase with the other.

Frequency Setting

A resistor, R

, connected between the FS/EN pin and ground

sets the frequency of the internal oscillator. Tying the FS/EN

pin to ground disables the oscillator, thus shutting down the

converter. The resistor can be calculated given the desired

channel switching frequency, F

Figure 5 provides a graph of oscillator frequency vs R

. The

maximum recommended channel frequency is 1.5MHz.

Reference Voltage

An internal 0.8V reference is used for both PWM duty cycle

determination as well as output voltage protection. The

reference is trimmed such that the system, including

amplifier offset voltages, is accurate to ±

1% over

temperature range.

Fault Protection

The ISL6558 protects the load device from damaging stress

levels. The overcurrent trip point is integral in preventing

output shorts of varying degrees from causing current spikes

which would damage a load device. The output voltage

detection features insure a safe window of operation for the

load device.

Overcurrent

The R

ISEN

resistor scales the voltage sampled across the

lower MOSFET and provides current feedback proportional

to the output current of each active channel. The ISEN

currents from all the active channels are averaged together

to form a scaled version of the total output current, I

TOTAL

PWM1, 5V/DIV

FIGURE 4. FOUR ACTIVE CHANNEL PWM DRIVE SIGNALS

1ms/DIV

PWM3, 5V/DIV

PWM4, 5V/DIV

PWM2, 5V/DIV

10.9 1.1 F

log–

(EQ. 5)

50 100

20 200 500 1,000

2,000

100

200

500

1,000

- kW

CHANNEL OSCILLATOR FREQUENCY, F

, [kHz]

FIGURE 5. OSCILLATOR FREQUENCY vs R

TOTAL

ISEN1

TRIP

82.5A

FIGURE 6. INTERNAL OVERCURRENT DETECTION

CIRCUITRY



n = ACTIVE CHANNELS

ISEN4

ISL6558

ISEN3

ISEN2

FIGURE 7. OVERCURRENT OPERATION

10ms/DIV

OUT

(5A/DIV)

OUT

(1V/DIV)

SHORT APPLIED

SHORT REMOVED

PGOOD (5V/DIV)

ISL6558

FN9027.13

August 28, 2015

See Figure 6. I

TOTAL

is compared with an internally

generated overcurrent trip current, I

TRIP

. The overcurrent

trip current source is trimmed to 82.5A. If I

TOTAL

exceeds

the I

TRIP

level, then the controller forces all PWM outputs

into three-state. This condition results in the HIP660x gate

drivers removing drive to the MOSFETs. The VSEN voltage

will begin to fall and once it descends below the PGOOD falling

threshold, the PGOOD signal transitions low.

A delay time, equal to the soft-start interval, is entered to

allow the disturbance to clear. After the delay time, the

controller then initiates a second soft-start interval. If the

output voltage comes up and regulation is achieved,

PGOOD transitions high. If the OC trip current is exceeded

during the soft start interval, the controller will again shut

down PWM operation and three-state the drivers. The

PGOOD signal will remain low and the soft-start interval will

be allowed to expire. Another soft-start interval will be

initiated after the delay interval. If an overcurrent trip occurs

again, this same cycle repeats until the fault is removed. The

OC function is shown in Figure 7 for a hard short of the

output which is applied for only a brief moment. The

converter quickly detects the short and attempts to restart

twice before the short is removed.

Overcurrent protection reduces the regulator RMS output

current under worst case conditions to 95% of the full load

current.

SELECTING R

ISEN

The procedure for determining the value of R

ISEN

is to

insure that it scales a channel’s maximum output current to

50A. This will insure that the overcurrent trip point is

properly detected when a current limit of 165% of the

converter’s full load current is breached. The ISEN resistor

can be calculated as follows:

where I

is the maximum output current demanded by the

load device and ‘n’ is the number of active channels.

OC TRIP LEVEL ADJUSTMENT

Setting the full load reference current, I

TOTAL

, to 50A is

recommended for most applications. The ratio between the

desired full load reference current and the internally set

overcurrent trip current is the overcurrent trip ratio, K

. For

those applications where an OC trip level of 1.65 times

TOTAL

is insufficient, the full load reference current can be

scaled differently. Care must be taken in selection of certain

components once the desired OC trip ratio is determined.

The new overcurrent trip ratio is then used to calculate the

ISEN resistors for the new full load reference current.

One commonly over looked component which will change

due to the new overcurrent trip ratio is the feedback resistor,

Temperature effects of the MOSFET r

DS(ON)

must be

reviewed when changing the overcurrent trip level.

Output Voltage Monitoring

The output voltage must be tied to the VSEN pin to provide

feedback used to create a window of operation. If the output

voltage is not the reference voltage of 0.8V, it must be scaled

externally down to this level. The VSEN voltage is then

compared with two set voltage levels which indicate an

overvoltage or undervoltage condition of the output. Violating

either of these conditions results in the PGOOD pin output

toggling low to indicate a problem with the output voltage.

OVERVOLTAGE

The VSEN voltage is compared with an internal overvoltage

protection (OVP) reference set to 115% of the internal

reference. If the VSEN voltage exceeds the OVP reference,

the comparator simultaneously sets the OV latch and

triggers the PWM output low. The drivers turn on the lower

MOSFETs, shunting the converter output to ground. Once

the output voltage falls below the nominal output voltage, the

PWM outputs are placed in three-state. This prevents

dumping of the output capacitors back through the lower

MOSFETs. If the overvoltage conditions persist, the PWM

outputs are cycled between the two states similar to a

hysteretic regulator. The OV latch can only be reset by

cycling the VCC supply voltage to initiate a POR and begin a

soft-start interval.

UNDERVOLTAGE

The VSEN voltage is also compared to a undervoltage (UV)

reference which is set to 90% of the internal reference. If the

VSEN voltage is below the UV reference, the power good

monitor triggers PGOOD to go low. The UV comparator does

not influence converter operation.

VSEN SCALING

The output voltage, V

OUT

, must be fed back to the VSEN pin

separately from the feedback components to the FB pin. If

VSEN and FB are tied together, the error amplifier will hold

the VSEN voltage at the reference level while the actual

output voltage level could be much different. This would

mask the output voltage and prevent the protection features

from reacting to undervoltage or overvoltage conditions at

the proper time.

ISEN

---------x

DS ON

50A

-------------------------=

(EQ. 6)

82.5A

TOTAL

-----------------------=

(EQ. 7)

ISEN

---------x

DS ON

82.5A

-------------------------------------------=

(EQ. 8)

DROOP

82.5A

---------------------------------------------=

(EQ. 9)

ISL6558

FN9027.13

August 28, 2015

If the output voltage is not the same as the internal 0.8V

reference, then a resistor divider scaled like the FB resistors

is required as shown is Figure 8. Otherwise, the output

voltage should be tied directly back to the VSEN pin without

a resistor divider.

PGOOD SIGNAL

The undervoltage comparator and overvoltage latch feed

into the power good monitor and are NOR’d together. If

either indicates a fault, the power good monitor triggers the

PGOOD output low. A high on this open drain pin indicates

proper output voltage.

Application Guidelines

Layout Considerations

Layout is very important in high frequency switching

converter design. With MOSFETs switching efficiently at

greater than 100kHz, the resulting current transitions from

one device to another cause voltage spikes across the

interconnecting impedances and parasitic circuit elements.

These voltage spikes can degrade efficiency, radiate noise

into the circuit, and lead to device overvoltage stress.

Careful component layout and printed circuit design

minimizes the voltage spikes in the converter.

As an example, consider the turnoff transition of the PWM

upper MOSFET. Prior to turnoff, the upper MOSFET was

carrying the channel current. During turnoff, current stops

flowing in the upper MOSFET and is picked up by the lower

MOSFET. Any inductance in the switched current path

generates a large voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide circuit traces minimize the

magnitude of voltage spikes.

There are two sets of critical components in a DC-DC

converter using a ISL6558 controller and HIP660x gate

drivers. The switching components are the most critical

because they switch large amounts of energy, and therefore

tend to generate equally large amounts of noise. Next are

the small signal components which connect to sensitive

nodes or supply critical bypassing current and signal

coupling.

A multi-layer printed circuit board is recommended. Figure 9

shows the connections of the critical components for one

output channel of the converter. Note that capacitors C

and C

OUT

could each represent numerous physical

capacitors. Dedicate one solid layer, usually the middle layer

of the PC board, for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this

plane into smaller islands of common voltage levels. Keep

the metal runs from the PHASE terminal to the output

inductor short. The power plane should support the input

power and output power nodes. Use copper filled polygons

on the top and bottom circuit layers for the phase nodes.

Use the remaining printed circuit layers for small signal

wiring. The wiring traces from the HIP660x driver to the

power MOSFET gates and source should be sized to carry

at least 1A of current.

The switching components and HIP660x gate drivers should

be placed first. Locate the input capacitors close to the

power switches. Minimize the length of the connections

between the input capacitors, C

, and the power switches.

Position both the ceramic and bulk input capacitors as close

to the upper MOSFET drain as possible. Locate the output

inductors and output capacitors between the MOSFETs and

the load. Place the HIP660x gate drivers close to their

respective channel MOSFETs.

The critical small signal components include the bypass

capacitors for VCC on the ISL6558 controller as well as

those on VCC and PVCC of the HIP660x gate drivers.

Position the bypass capacitors, C

, close to the device

pins. It is especially important to place the feedback

resistors, R

and R

, and compensation components, R

and C

, associated with the input to the error amplifier close

to the FB and COMP pins. Care should be taken in routing

the current sense lines such that the ISEN resistors are

close to their respective pins on the controller. Resistor R

which sets the oscillator frequency, should be positioned

near the FS/EN pin.

VSEN

OUT

ISL6558

FIGURE 8. VSEN RESISTOR DIVIDER CONFIGURATION

DROOP

ISL6558

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ISL6558IRZ-TK

Mfr. #:

Buy ISL6558IRZ-TK

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers 2-4 PHS PWM CNTRLR NO DAC 20L 5X5 MLFP

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ISL6558IRZ-TK

ISL6558IRZ-TK

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