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MC14526BDW

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 8
1 Publication Order Number:
MC14526B/D
MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P−channel
and N−channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as
a negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge−Clocked Design: Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
• Asynchronous Preset Enable
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS
Rating Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
,
V
out
−0.5 to V
DD
+ 0.5 V
Input or Output Current
(DC or Transient) per Pin
I
in
, I
out
±10 mA
Power Dissipation per Package (Note 1) P
D
500 mW
Operating Temperature Range T
A
−55 to +125 °C
Storage Temperature Range T
stg
−65 to +150 °C
Lead Temperature
(8−Second Soldering)
T
L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
SOIC−16 WB
DW SUFFIX
CASE 751G
MARKING DIAGRAM
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
1
1
14526B
AWLYWWG
MC14526B
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2
FUNCTION TABLE
Inputs Output
Resulting
Function
Clock Reset Inhibit
Preset
Enable
Cascade
Feedback
“0”
X
X
X
H
H
H
X
X
X
L
H
X
L
L
H
L
H
H
Asynchronous reset*
Asynchronous reset
Asynchronous reset
X L X H X L Asynchronous preset
L
L
L
H L
L
X
X
L
L
Decrement inhibited
Decrement inhibited
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
No change** (inactive edge)
No change** (inactive edge)
Decrement**
Decrement**
X = Don’t Care
NOTES:
** Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
PIN DESCRIPTIONS
Preset Enable (Pin 3) — If Reset is low, a high level on the
Preset Enable input asynchronously loads the counter with
the programmed values on P0, P1, P2, and P3.
Inhibit (Pin 4) — A high level on the Inhibit input pre−
vents the Clock from decrementing the counter. With Clock
(pin 6) held high, Inhibit may be used as a negative edge clock
input.
Clock (Pin 6) — The counter decrements by one for each
rising edge of Clock. See the Function Table for level
requirements on the other inputs.
Reset (Pin 10) — A high level on Reset asynchronously
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
high, causes the “0” output to go high.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
other than all zeroes, the “0” output is valid after the rising
edge of Preset Enable (when Cascade Feedback is high). See
the Function Table.
Cascade Feedback (Pin 13) — If the Cascade Feedback
input is high, a high level is generated at the “0” output when
the count is all zeroes. If Cascade Feedback is low, the “0”
output depends on the Preset Enable input level. See the
Function Table.
P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
data inputs. P0 is the LSB.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the
synchronous counter outputs. Q0 is the LSB.
V
SS
(Pin 8) — The most negative power supply potential.
This pin is usually ground.
V
DD
(Pin 16) — The most positive power supply potential.
V
DD
may range from 3.0 to 18 V with respect to V
SS
.
STATE DIAGRAM
MC14526B
43210
15
14
13
12 11 10 9 8
7
6
5
MC14526B
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
DD
Vdc
−55°C 25°C 125°C
Characteristic Symbol Min Max Min Typ
(Note 2)
Max Min Max Unit
Output Voltage “0” Level
V
in
= V
DD
or 0
“1” Level
V
in
= 0 or V
DD
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
Output Voltage “0” Level
V
in
= V
DD
or 0
“1” Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
Input Voltage “0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc) Sin
k
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OH
5.0
5.0
10
15
−3.0
−0.64
−1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
mAdc
I
OL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current I
in
15 − ±0.1 − ±0.00001 ±0.1 − ±1.0
mAdc
Input Capacitance
(V
in
= 0)
C
in
− − − − 5.0 7.5 − − pF
Quiescent Current
(Per Package)
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent, Per Package)
(C
L
= 50 pF on all outputs, all buffers
switching)
5.0
10
15
I
T
= (1.7 mA/kHz) f + I
DD
I
T
= (3.4 mA/kHz) f + I
DD
I
T
= (5.1 mA/kHz) f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in mA (per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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MC14526BDW

Mfr. #:
Buy MC14526BDW
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 3-18V Presettable
Lifecycle:
New from this manufacturer.
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