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PI6C185-01QIEX

P1-P3P4-P6P7-P7
4
PS8318F 11/13/08
PI6C185-01
Precision 1-5 Clock Buffer
SDRAM Clock Buffer Operating Specification
DC Operating Specifications (V
DD
= +3.3V ±5%, T
A
= 0°C - 70°C)
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NIMHO
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TUO
V0.2=45–
Am
I
XAMHO
tnerrucpu-lluPV
TUO
V531.3=64–
I
NIMLO
tnerrucnwod-lluPV
TUO
V0.1=45
I
XAMLO
tnerrucnwod-lluPV
TUO
V4.0=35
t
HR
MARDSylnoMARDSetaregdeesirtuptuOV4.2-V4.0@%5±V3.35.14
sn/V
t
HF
MARDSylnoMARDSetaregdellaftuptuOV4.0-V4.2@%5±V3.35.14
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V
HI
egatloVhgiHtupnIV
DD
0.2V
DD
3.0+
V
V
LI
egatloVwoLtupnIV
SS
3.0–8.0
I
LI
tnerruCegakaeLtupnIV<0
NI
V<
DD
5-5+
μA
V
DD
%5±V3.3=
V
HO
egatloVhgiHtuptuOI
HO
Am1-=4.2
V
V
LO
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LO
Am1=4.0
C
NI
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Fp
C
TUO
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L
NIP
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T
A
erutarepmeTtneibmAwolfriAoN007Cº
AC Timing
Symbol Parameter 66 MHz 100 MHz 133 MHz Units
Min. Max. Min. Max. Min. Max.
T
DSKP
SDRAM CLK period 15.0 15.5 10.0 10.5 7.5 8.0 ns
T
SDKH
SDRAM CLK high time 5.6 3.3 2.2 ns
T
SDKL
SDRAM CLK low time 5.3 3.1 2.0 ns
T
SDRISE
SDRAM CLK rise time 1.5 4.0 1.5 4.0 1.4 4.0 V/ns
T
SDFALL
SDRAM CLK fall time 1.5 4.0 1.5 4.0 1.4 4.0 V/ns
t
PLH
SDRAM Buffer LH prop delay 1.0 5.5 1.0 5.0 1.0 5.0 ns
t
PHL
SDRAM Buffer HL prop delay 1.0 5.5 1.0 5.0 1.0 5.0 ns
DutyCycle Measured at 1.5V 45 55 45 55 45 55 %
tSDSKW SDRAM Output to Output Skew 250 250 250 ps
08-0298
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PS8318F 11/13/08
PI6C185-01
Precision 1-5 Clock Buffer
1.5V 1.5V
t
phl
t
plh
1.5V 1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place R
S
series resistors and CI capacitors as close as possible to the respective clock pins. Typical
value for CI is 10 pF. R
S
Series resistor value can be increased to reduce EMI provided that the rise
and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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MARDS0203FpnoitacificepSMMIDMARDS
08-0298
6
PS8318F 11/13/08
PI6C185-01
Precision 1-5 Clock Buffer
Packaging Mechanical: 16-Pin TSSOP (L)
Figure 2. Design Guidelines
SDRAM
R
5
C
L
SDRAM
DIMM
Spec.
100/66 MHz
Clock from
Chipset
s
1
DESCRIPTION: 16-Pin, 173-Mil Wide, TSSOP
PACKAGE CODE: L
DOCUMENT CONTROL NO.
PD - 1310
REVISION: E
DATE: 03/09/05
Note:
1. Package Outline Exclusive of Mold Flash and Metal Burr
2. Controlling dimentions in millimeters
3. Ref: JEDEC MO-153F/AB
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
.193
.201
.047
max.
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.004
.008
.252
BSC
1
16
.169
.177
0.05
0.15
6.4
0.45
0.75
0.09
0.20
4.3
4.5
1.20
4.9
5.1
0.65
0.19
0.30
.007
.012
08-0298
P1-P3P4-P6P7-P7

PI6C185-01QIEX

Mfr. #:
Buy PI6C185-01QIEX
Manufacturer:
Diodes Incorporated
Description:
Clock Buffer Precision 1:5 Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
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