AD7788/AD7789 Data Sheet
Rev. C | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
03539-007
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0408020 60 100 120 140
dB
160
0
FREQUENCY (Hz)
Figure 6. Frequency Response with 16.6 Hz Update Rate
03539-008
0
10
20
30
40
50
60
70
8388591
OCCURENCE
8388625
CODE
V
DD
= 3V
V
REF
= 2.048V
T
A
= 25°C
RMS NOISE = 1.25µV
Figure 7. AD7789 Noise Histogram
03539-009
8388591
0 200 400 600 800
CODE
1000
8388625
READ NO.
V
DD
= 3V, V
REF
= 2.048V,
T
A
= 25°C, RMS NOISE = 1.25µV
Figure 8. AD7789 Noise Plot
03539-013
0
0.5
1.0
1.5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
RMS NOISE (µV)
5.0
3.0
2.5
2.0
V
REF
(V)
V
DD
= 5V
UPDATE RATE = 16.6Hz
T
A
= 25°C
Figure 9. AD7788/AD7789 Noise vs. V
REF
Data Sheet AD7788/AD7789
Rev. C | Page 11 of 20
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip
registers, which are described on the following pages. In the
following descriptions, set implies a Logic 1 state and cleared
implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER
(RS1, RS0 = 0, 0)
The communications register is an 8-bit, write only register. All
communications to the device must start with a write operation
to the communications register. The data written to the commun-
ications register determines whether the next operation is a read
or write operation, and to which register this operation takes
place.
For read or write operations, once the subsequent read or write
operation to the selected register is complete, the interface returns
to where it expects a write operation to the communications
register. This is the default state of the interface and, on power-up
or after a reset, the ADC is in this default state waiting for a write
operation to the communications register. In situations where the
interface sequence is lost, a write operation of at least 32 serial
clock cycles with DIN high returns the ADC to this default state
by resetting the entire device. Table 7 outlines the bit designations
for the communications register. CR0 through CR7 indicate the
bit location, CR denoting the bits are in the communications
register. CR7 denotes the first bit of the data stream. The number in
parentheses indicates the power-on/reset default status of that bit.
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
WEN(0)
0(0) RS1(0) RS0(0)
R/W(0)
CREAD(0) CH1(0) CH0(0)
Table 7. Communications Register Bit Designations
Bit Location Bit Name Description
CR7
WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the device does not clock on to subsequent bits in the register. It stays at
this bit location until a 0 is written to this bit. Once a 0 is written to the
WEN bit, the next seven bits are
loaded to the communications register.
CR6 0 This bit must be programmed with a Logic 0 for correct operation.
CR5 to CR4 RS1 to RS0
Register Address Bits. These address bits are used to select which of the ADC registers are being selected
during this serial interface communication (see Table 8).
CR3
R/
W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
CR2 CREAD
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read, that is, the contents of the data
register are placed on the DOUT/
RDY pin automatically when the SCLK pulses are applied. The communications
register does not have to be written to for data reads. To enable continuous read mode, the instruction
001111XX must be written to the communications register. To exit the continuous read mode, the
instruction 001110XX must be written to the communications register while the DOUT/
RDY pin is low.
While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN.
Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.
CR1 to CR0
CH1 to CH0
These bits are used to select the analog input channel. The differential channel can be selected
AIN(+)/AIN() or an internal short AIN(−)/AIN(−) can be selected. Alternatively, the power supply can be
selected, that is, the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog-to-digital
conversion. Any change in channel resets the filter and a new conversion is started.
AD7788/AD7789 Data Sheet
Rev. C | Page 12 of 20
Table 8. Register Selection
RS1 RS0 Register Register Size
0 0 Communications register during a write operation 8-bit
0 0 Status register during a read operation 8-bit
0 1 Mode register 8-bit
1 0 Reserved 8-bit
1 1 Data register 16-bit (AD7788)
24-bit (AD7789)
Table 9. Channel Selection
CH1 CH0 Channel
0 0 AIN(+)AIN()
0 1 Reserved
1 0 AIN(−) − AIN()
1
1
V
DD
monitor
STATUS REGISTER
(RS1, RS0 = 0, 0; Power-On/Reset = 0x88 for AD7788 and 0x8C for AD7789)
The status register is an 8-bit, read only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS1 and Bit RS0 with 0. Tabl e 10 outlines the bit designations for the status register.
SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number(s) in parentheses indicates the power-on/reset default status of that bit.
MSB LSB
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
RDY(1)
ERR(0) 0(0) 0(0) 1(1) WL(1/0) CH1(0) CH0(0)
Table 10. Status Register Bit Designations
Bit Location Bit Name Description
SR7
RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to tell the user not to read the conversion data. It is also set when the device is
placed in power-down mode. The end of a conversion is indicated by the DOUT/
RDY pin. This pin can be
used as an alternative to the status register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, under-
range. Cleared by a write operation to start a conversion.
SR5 0 This bit is cleared automatically.
SR4 0 This bit is cleared automatically.
SR3
1
This bit is set automatically.
SR2 WL
AD7788/AD7789 Identifier. This bit is cleared automatically if the device is an AD7788 and it is set
automatically if the device is an AD7789. This bit is used to distinguish between the AD7788 and AD7789.
SR1 to SR0 CH1 to CH0 These bits indicate which channel is being converted by the ADC.

AD7788ARMZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit SGL-Ch Ultra Low Power
Lifecycle:
New from this manufacturer.
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