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XC17S50ASO20C

P1-P3P4-P6P7-P8
DS078 (v1.10) June 25, 2007 www.xilinx.com
Product Specification 1
© 2000-2002, 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan™-II/Spartan-IIE FPGA devices
• Simple interface to the Spartan device
• Programmable reset polarity (active High or active Low)
• Low-power CMOS floating gate process
• 3.3V PROM
• Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages
• Programming support by leading programmer
manufacturers
• Design support using the Xilinx Alliance and
Foundation™ series software packages
• Guaranteed 20-year life data retention
• Pb-free (RoHS-compliant) packaging available
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
the Spartan device D
IN
pin. The Spartan device generates
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
0
Spartan-II/Spartan-IIE Family OTP
Configuration PROMs (XC17S00A)
DS078 (v1.10) June 25, 2007
05
Product Specification
R
Spartan-II/IIE FPGA Configuration Bits Compatible Spartan-II/IIE PROM
XC2S15 197,696 XC17S15A
XC2S30 336,768 XC17S30A
XC2S50 559,200 XC17S50A
XC2S100 781,216 XC17S100A
XC2S150 1,040,096 XC17S150A
XC2S200 1,335,840 XC17S200A
XC2S50E 630,048 XC17S50A
XC2S100E 863,840 XC17S100A
XC2S150E
(1)
1,134,496 XC17S200A
XC2S200E 1,442,016 XC17S200A
XC2S300E 1,875,648 XC17S300A
XC2S400E 2,693,440 XC17V04
(2)
XC2S600E 3,961,632 XC17V04
(2)
Notes:
1. Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
2. See XC17V00 series configuration PROMs data sheet at: http://direct.xilinx.com/bvdocs/publications/ds073.pdf
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
DS078 (v1.10) June 25, 2007 www.xilinx.com
Product Specification 2
R
Pin Description
Pins not listed are no connects.
Pinout Diagrams
Pin Name
8-pin
PDIP
(PD8/PDG8)
and
VOIC/TSOP
(VO8/VOG8)
20-pin
SOIC
(SO20)
44-pin
VQFP
(VQ44)
Pin Description
DATA 1 1 40 • Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to
be either active High or active Low.
CLK 2 3 43 • Each rising edge on the CLK input increments the internal address
counter, if both CE and OE are active.
RESET/OE
(OE/RESET
)
3813• When High, this input holds the address counter reset and puts the
DATA output in a high-impedance state. The polarity of this input pin is
programmable as either RESET/OE
or OE/RESET. To avoid confusion,
this document describes the pin as RESET/OE, although the opposite
polarity is possible on all devices. When RESET is active, the address
counter is held at zero, and the DATA output is in a high-impedance
state. The polarity of this input is programmable. The default is active-
High RESET, but the preferred option is active Low RESET
, because it
can be connected to the FPGAs INIT pin and a pull-up resistor.
• The polarity of this pin is controlled in the programmer interface. This
input pin is easily inverted using the Xilinx HW-130 programmer software.
Third-party programmers have different methods to invert this pin.
CE 41015• When High, this pin resets the internal address counter, puts the DATA
output in a high-impedance state, and forces the device into low-I
CC
standby mode.
GND 5 11 18, 41 • GND is the ground connection.
V
CC
7, 8 18, 20 38, 35 • The V
CC
pins are to be connected to the positive voltage supply.
PD8/PDG8
VO8/VOG8
Top View
ds078_04_061805
8
7
6
5
1
2
3
4
VCC
VCC
NC
GND
DATA (D0)
CLK
OE/RESET
CE
ds078_05_061805
SO20
Top View
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OE/RESET
NC
CE
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VCC
NC
ds073_06_061805
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
DS078 (v1.10) June 25, 2007 www.xilinx.com
Product Specification 3
R
Controlling PROMs
• Connecting the Spartan device with the PROM:
• The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
• The Master Spartan device CCLK output drives the
CLK input of the PROM.
• The RESET
/OE input of the PROM is connected to the
INIT
pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a V
CC
glitch.
• The CE
input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE
can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial mode provides a simple configuration
interface (Figure 1). Only a serial data line, two control lines,
and a clock line are required to configure the Spartan
device. Data from the PROM is read sequentially, accessed
via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE family takes care of this
automatically with an on-chip pull-up/down resistor or
keeper circuit.
The one-time-programmable XC17S00A PROM in
Figure 1, page 3 supports automatic loading of
configuration programs. An early DONE inhibits the PROM
data output one CCLK cycle before the Spartan FPGA I/Os
become active.
Figure 1: XC17S00A PROM Connections to FPGA in Master Serial Mode
D
IN
CCLK
INIT
DONE
XC17S00A
PROM
DATA
CLK
CE
Spartan-II/
Spartan-IIE
Master Serial
DS078_01_061107
OE/RESET
M0
M1
M2
3.3V
V
CC
V
CC
3.3V
3.3 KΩ
Notes:
1. If the DriveDone configuration option is not active, pull up DONE with a 3.3 kΩ resistor.
3.3 KΩ
P1-P3P4-P6P7-P8

XC17S50ASO20C

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Manufacturer:
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Description:
IC PROM SER 50000 C-TEMP 20-SOIC
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