ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
ADJMP
Noise Rectifier adjustment
through Multipath
8)
Signal PEAK in
Testmode
MPNB = 00
8)
(c) 0.3 (c) V/ms
MPNB = 01
8)
(c) 0.5 (c) V/ms
MPNB = 10
8)
(c) 0.7 (c) V/ms
MPNB = 11
8)
(c) 0.9 (c) V/ms
0) All Thresholds are measured using a pulse with T
R
=2
µ
s, T
HIGH
= 2
µ
s and T
F
= 10
µ
s. The repetition rate must not increase the PEAK voltage.
1) NBT represents the Noiseblanker Byte bits D
2
, D
0
for the noise blanker trigger threshold
2) NAT represents the Noiseblanker Byte bit pair D
4
, D
3
for the noise controlled triggeradjustment
3) OVD represents the Noiseblanker Byte bit pair D
7
, D
6
for the over deviation detector
4) FSC represents the Fieldstrength Byte bit pair D
1
, D
0
for the fieldstrength control
5) BLT represents the Speaker RR Byte bit pair D
7
, D
6
for the blanktime adjustment
6) NRD represents the Configuration-Byte bit pair D
1
, D
0
for the noise rectifier discharge-adjustment
7) PCH represents the Stereodecoder-Byte bit D
5
for the noise rectifier charge-current adjustment
8) MPNB represents the HighCut-Byte bit D
7
and the Fieldstrength-Byte D
7
for the noise rectifier multipath adjustment
65mV
30mV
8 STEPS
NOISE CONTROLLED
TRIG. THRESHOLD
MIN. TRIG. THRESHOLD
260mV(00)
220mV(01)
180mV(10)
140mV(11)
0.9V
VTH
1.5V
V
PEAK(V)
D97AU648
Figure 1. Trigger Threshold vs.V
PEAK
V
PEAK
(V
OP
)
D97AU649
20
DEVIATION(KHz)
0.9
1.2
2.0
2.8
DETECTOR OFF (11)
32.5 45 75
10
01
00
Figure 2. Deviation Controlled Trigger Adjust-
ment
V
OP
V
IN
DC
T
R
T
HIGH
T
F
Time
D97AU636
TDA7400D
10/28
Obsolete Product(s) - Obsolete Product(s)
2.4V(00)
0.9V
V
PEAK
E'
D97AU650
1.9V(01)
1.4V(10)
MONO STEREO
noisy signal good signal
ATC_SB OFF (11)
NOISE
»3V
Figure 3. Fieldstrength Controlled Trigger Adjustment
Multipath Detector
Internal 19kHz band pass filter
Programmable band pass and rectifier gain
two pin solution fully independent usable for
external programming
selectable internal influence on Stereoblend
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
f
CMP
Center Frequency of Multipath-
Bandpass
stereodecoder locked on Pilottono 19 KHz
G
BPMP
Bandpass Gain bits D
2
, D
1
configuration byte = 00 6 dB
bits D
2
, D
1
configuration byte = 10 12 dB
bits D
2
, D
1
configuration byte = 01 16 dB
bits D
2
, D
1
configuration byte = 11 18 dB
G
RECTMP
Rectifier Gain bits D
7
, D
6
configuration byte = 00 7.6 dB
bits D
7
, D
6
configuration byte = 01 4.6 dB
bits D
7
, D
6
configuration byte = 10 0 dB
bits D
7
, D
6
configuration byte = 11 off dB
I
CHMP
Rectifier Charge Current bit D
5
configuration byte = 0 0.5
µ
A
bit D
5
configuration byte = 1 1.0
µ
A
I
DISMP
Rectifier Discharge Current 0.5 1 1.5 mA
Quality Detector
Symbol Parameter Test Condition Min. Typ. Max.
Unit
A Multipath Influence Factor bit D
7
High-Cut byte +
bit D
7
Fieldstrength byte +
00
01
10
11
0.7
0.85
1.00
1.15
TDA7400D
11/28
Obsolete Product(s) - Obsolete Product(s)
DESCRIPTION OF THE AUDIOPROCESSOR
PART
Input Multiplexer
CD quasi differential
Cassette stereo
Phone differential
AM mono
Stereodecoder input.
Input stages
Most of the input stages have remained the same
as in preceeding ST audioprocessors with excep-
tion of the CD inputs (see figure 4).
In the meantime there are some CD players in
the market having a significant high source im-
pedance which affects strongly the common-
mode rejection of the normal differential input
stage. The additional buffer of the CD input
avoids this drawback and offers the full common-
mode rejection even with those CD players.
The output of the Cd stage is permanently avail-
able of the Cd out-pins
AutoZero
In order to reduce the number of pins there is no
AC coupling between the In-Gain and the follow-
ing stage, so that any offset generated by or be-
fore the In-Gain stage would be transferred or
even amplified to the output.
To avoid that effect a special offset cancellation
stage called AutoZero is implemented.
This stage is located before the volume-block to
eliminate all offsets generated by the Stereode-
coder, the Input Stage and the In-Gain (Please
notice that externally generated offsets, e.g. gen-
erated through the leakage current of the cou-
pling capacitors, are not cancelled).
The auto-zeroing is started every time the DATA-
BYTE 0 is selected and takes a time of max.
0.3ms. To avoid audible clicks the audioproces-
sor is muted before the volume stage during this
time.
AutoZero Remain
In some cases, for example if the µP is executing
a refresh cycle of the I
2
C bus programming, it is
not useful to start a new AutoZero action because
no new source is selected and an undesired mute
would appear at the outputs. For such applica-
tions the TDA7400D could be switched in the
"Auto Zero Remain mode" (Bit 6 of the subad-
dress byte). If this bit is set to high, the DAT-
ABYTE 0 could be loaded without invoking the
AutoZero and the old adjustment value remains.
Multiplexer Output
The output signal of the Input Multiplexer is avail-
able at separate pins (please see the Blockdia-
gram). This signal represents the input signal am-
plifier by the In Gain stage and is also going into
the Mixer stage.
Softmute
The digitally controlled softmute stage allows
muting/demuting the signal with a I
2
C bus pro-
grammable slope. The mute process can either
be activated by the softmute pin or by the I
2
C
bus. The slope is realized in a special S shaped
curve to mute slow in the critical regions (see fig-
ure 5).
15K 15K
100K
CD+
CD-
15K 15K
+
-
15K 15K
PHONE+
PHONE-
15K 15K
+
-
D98AU854A
100K
100K
100K
STEREODECODER
IN GAIN
CASSETTE
AM
MPX
1
1
100K
CD OUT
Figure 4. Input stages
TDA7400D
12/28
Obsolete Product(s) - Obsolete Product(s)

TDA7400DTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Audio DSPs ADV CAR SGNL PROCESR
Lifecycle:
New from this manufacturer.
Delivery:
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