7
Slow Ramping Current Trip Level CT/CR di/dt = 0.001A/s, Current Trip Level/Current
Regulation Level
-90-%
Current Trip Level Temp Coeff. M12VCT_t dCT/85°C - 0.1 - mA/°C
Gate Turn-Off Time t
OFFM12VG
C
M12VG
= 0.005F, M12VG Falling 90% to 10% - 330 - ns
Gate Response Time To Overcurrent t
OC2M12VG
-11s
Gate Response Time to WOC t
WOC2M12VG
- 400 - ns
Gate Output Charge Current IC
M12VG
ENABLE = High, V
M12VG
= -10V - 102 - A
Vout Turn-On Time t
ONM12VO
-12V Falling 90% - 10%, C
M12VO
= 50F, R
L
= 120 -11-ms
Vout Turn-On Time t
ONM12VO
-12V Falling 90% - 10%, C
M12VO
= 150F, R
L
=120 -35-ms
Vout Turn-Off Time t
OFFM12VO
-12V Rising 10% - 90%, C
M12VO
= 150F, R
L
= 120 -40-ms
Vout Turn-Off Time WOC t
OFFM12VOWOC
-12V Rising 10% - 90%, C
M12VO
= 150F, R
L
= 120 -15-s
Vout Turn-Off Voltage V
OFFM12VO
Vout when off - -0.6 - V
M12VIN Input Bias Current IB
M12VIN
ENABLE = High 4.5 5.3 7 mA
CONTROL AND I/O PINS
CRSET Current Source I
CRSET
90 100 110 A
Rising ENABLE Threshold Voltage V
TH_EN_L2H
1.5 1.7 2.0 V
Falling ENABLE Threshold Voltage V
TH_EN_H2L
1.2 1.5 1.9 V
ENABLE Threshold Voltage Hysteresis V
TH_EN_HYS
-0.20.3V
Enable to Output Turn-on Prop. Delay Tpd_EN Enable high to start of output turn=on - 2 - ms
Power Good Output Low Voltage V
PG,L
I
PG
= 5mA - 0.6 0.75 V
Power Good Output Pull-down Current I
PG
-40-mA
Power Good to Vout Falling Response
Time
t
UV2PG_fall
Vout < UV Vth to PG low - 500 - ns
Power Good to Vout Rising Response
Time
t
UV2PG_rise
Vout >UV Vth to PG high - 8 - ms
FAULTN Output Low Voltage V
FLTN,L
I
FLTN
= 5mA - 0.6 0.75 V
FAULTN Output Pull-down Current I
FLTN
-40-mA
FAULTN Output Response Time t
OC2FLTN
C
TIM
_Vth to FLTN low - - 1 µs
CRTIM Charging Current CRTIM_ichg0 V
CTIM
= 0V - 26 - A
Current Regulation Time-Out Threshold CRTIM_Vth CTIM Voltage 2.74 2.83 2.92 V
BIAS
12V Lock Out Threshold V
POR,THrise
V
CC
Voltage Rising 9.88 10.1 10.5 V
12V Power On Reset Threshold V
POR,THfall
V
CC
Voltage Falling 9.17 9.3 9.43 V
12V Reset Threshold Hysteresis V
POR,HYS
-0.69- V
12V Disabled Supply Current I
DIS
12VIN, EN = 0V - 3.3 6 mA
Electrical Specifications Nominal 5.0V and 3.3V Input Supply Voltages,
12VI = 12V, M12VI = -12V, T
A
= T
J
= 0 to 75°C, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL6111
8
Introduction
The ISL6111, is an IC device designed to provide control
and protection of the four legacy PCI power supplies (+12V,
-12V, +5V and +3.3V) for a single PCI or PCI-X slot. Unlike
the widely used HIP1011, this device employs an active
current regulation (CR) method to provide system
protection against load faults.
Figure 1 illustrates the typical implementation of the ISL6111.
Key Feature Description and Operation
The ISL6111, 2 power MOSFETs and a few passive
components as configured in Figure 1, completes a power
control solution for the legacy supplies to a PCI slot. It
provides protection via a programmable maximum current
regulation (CR) level to the load for each supply. For the
3.3V and 5V supplies, current monitoring is provided by
sensing the voltage across external current-sense resistors,
and CR protection is provided by active voltage modulation
of external N-Channel MOSFETs. For the +12V and -12V
supplies, current monitoring and CR protection are provided
internally.
During initial power-up of the main bias supply pins (12VI),
the ENABLE input function is inhibited from turning on the
switches, this latch is held in the reset state until the bias
voltage is greater than 10V (POR rising). Additionally the
power good and fault reporting functions are also disabled at
this time and during the soft start duration.
During turn-on of the supplies onto their capacitive loads the
current limiting fail-safe is engaged, this limited current gives
a voltage ramp-up slew rate centered within the PCI specs.
As the startup is current-limited, the CRTIM timer is engaged
during the entire startup, as it should be. This eliminates the
otherwise destructive case of starting up into a dead short.
Depending on loading, the positive 3 supplies will start up
and exit current limiting in about 6ms -10ms. The -12V
supply will take much longer, as it has a fraction of the
available charging current into a potentially relatively very
large load capacitance, and the voltage has to slew to -12V.
The -12V turn-on duration can thus be several times as long
extending to ~50ms for a very capacitive (147µF) load in
conjunction with a maximum current load. In addition if the
CR level is too low then it’s possible that the load
capacitance cannot fully charge in the allowed for time, this
is the consequence of the current regulation limiting
protection.
Once turned on, any subsequent over current (OC) condition
on any output results in the affected switch (external or
internal) to be put into its linear mode of operation, and the
current is regulated to the level determined by the choice of
external CRSET resistor value. An OC condition is defined
as a current level > the programmed CR level and that
transitions through the CR level with a quick ramp, <0.5µs.
This CR level is maintained until the OC condition passes or
the CR duration expires, whichever comes first. The CR
duration is user defined by the capacitor value on the CRTIM
pin. Once in CR mode, the CRTIM pin charges the capacitor
with a 20µA current until the voltage on CRTIM rises to
~2.8V, at which time a turn-off latch is set on all 4 power FET
switches. Also at this time the open drain fault (FLTN) output
is pulled low signalling a latched off state. After a fault has
been asserted and FLTN is latched low, cycling ENABLE low
will clear the FLTN latch.
On-chip references in the ISL6111 are used to monitor the
+5V, +3.3V and +12V outputs for under voltage (UV)
conditions. Once an UV condition is present the open drain
power good (PGOOD) output will pull low to indicate this.
Customizing Circuit Performance
Setting Current Regulation (CR) Level
The ISL6111 allows for easy and simultaneous custom
programming of the CR levels of all 4 supplies by simply
changing the resistor value between CRSET, (pin 18), and
ground. The R
CRSET
value and the CRSET 100A current
source create a reference voltage that is used in each of four
comparators. The IR voltages developed across the 3.3V
and 5V sense resistors are applied to the inputs of their
respective comparators opposite this reference voltage. The
+12V and -12V currents are sensed internally with pilot
devices. Because of the internal current monitoring of the
+12V and -12V switches, their programming flexibility is
limited to R
CRSET
changes whereas the 3.3V and 5V over
current regulation levels depend on both R
CRSET
, and the
value chosen for each sense resistor.
See Table 1 to determine CR protection levels relative to
choice of R
CRSET
and R
SENSE
values.
Over current design guidelines and recommendations are as
follows:
1. For PCI applications, set R
CRSET
to 4.22k, and use
5m 1% sense resistors (see Figure 20). This R
CRSET
value provides a nominal current trip level 110% to 130%
higher than the maximum specified current, to ensure full
current range use by the PCI load. The ISL6111 will trip
off on a slow increasing current ramp approximately 10%
to 20% lower than set CR level.
2. For non PCI specified applications, the following
precautions and limitations apply:
A. Do not exceed the maximum power of the integrated
NMOS and PMOS. High power dissipation must be
coupled with effective thermal management and prudent
CR durations. The integrated PMOS has an r
DS(ON)
of
0.35. With 2.5A of steady load current on the PMOS
device the power dissipation is 2.2W. The thermal
impedance of the package is 31 degrees Celsius per
watt, resulting in a 68°C die temp rise thus limiting the
average DC current on the 12V supply to about 2.5A
maximum at +85°C ambient and imposing an upper limit
on the R
OCSET
resistor. Do not use an R
CRSET
resistor
greater than 15k.
ISL6111
9
The average current on the -12V supply should not
exceed 0.8A. Since the thermal restrictions on the +12V
supply are more severe, the +12V supply restricts the use
of the ISL6111 to applications where the 12V supplies
draw relatively little current. Since both supplies only have
one degree of freedom, the value of R
OCSET
, the
flexibility of programming is quite limited. For applications
where more power is required on the +12V supply,
contact your local Intersil sales representative for
information on other Hot Plug solutions.
B. Do not try to sense voltages across the external sense
resistors that are less than 20mV as spurious faults due
to noise and comparator input sensitivity may result. The
minimum recommended R
CRSET
value is 3.0k. This
will set the nominal OC voltage thresholds at 39mV and
26mV for the 3.3V and 5V comparators respectively.
C. Minimize V
RSENSE
so as to not significantly reduce the
voltage delivered to the adapter card. Remember PCB
trace and connector distribution voltage losses also need
to be considered. Make sure that the R
SENSE
resistor
can adequately handle the dissipated power. For best
results use a 1% precision resistor with a low temperature
coefficient.
D. Minimize external FET r
DS(ON)
. Low r
DS(ON)
or multiple
MOSFETs in parallel are recommended.
Current Regulation Delay Time to Latch-Off
The CR time delay to latch-off, allows for a predetermined
delay from the start of CR, to the simultaneous latch-off of all
four supply switches to the load. This delay period is set by
the capacitor value to ground from the CRTIM pin. This
feature allows the ISL6111 to provide a current regulated soft
start into all loads, and to delay immediate latch-off of the
bus supply switches thus ignoring transient OC conditions.
See Table 2. for CR duration vs CRTIM capacitance value.
Caution: An additional concern about long CR durations
along with MB supply droop is power-FET survivability. The
primary purpose of a protection device such as the ISL6111
is to quickly isolate a faulted card from the voltage bus.
Delaying the time to latch-off works against this primary
concern so understand the limitations and realities. Since we
use the same CRTIM cap timing cap for all supplies, we
have to set that cap to a size large enough to allow the -12V
to start up under the worst load for a given system. If we set
this to a 75ms duration, then this 75ms time-out duration will
also be used when one of the higher power supplies goes
into current limiting after startup is complete. The highest
power supplies, the 3.3V and 5V each run to a maximum of
25W, as allowed by the PCI spec. If our overcurrent duration
is set to 75ms, then theoretically (but extremely unlikely)
more than 25W can be dissipated in the external FET for that
whole duration. The ISL6111 has a way over-current "WOC"
circuit that faults the chip off instantly if this theoretical dead
short happens so quickly that the current limiting circuitry
can't keep up. In reality, overcurrent is more likely to not be a
zero-ohm short, and only a fraction of the power is
dissipated in the FET.
Ensure adequate sizing of external FETs to carry additional
current during CR period in linear operation. By looking at
the SOA of the Siliconix Si4404DY FET and even
presupposing the full 25W for 100ms duration for a single
pulse is not an issue with this power FET. This FET is
representative of FETs for a PCI application. If for a higher
power non PCI design, consult the MOSFET vendor SOA
curves.
Application Considerations
Soft Start and Turn-Off Considerations
The ISL6111 does allow the user to select the rate of ramp
up on the voltage supplies. This start-up ramp minimizes in-
rush current at start-up while the on card bulk capacitors
charge. The ramp is created by placing capacitors on
M12VG, 3VG and 5VG to ground. These capacitors are each
charged up by a nominal 25A current during turn on. The
+12VO has internal current controlled ramping circuitry. The
same value for all gate timing capacitors is recommended.
The gate capacitors must be discharged when a fault is
detected to turn off the power FETs thus, larger caps slow
the response time. If the gate capacitors are too large the
ISL6111 may not be able to adequately protect the bus or the
power FETs. The ISL6111 has internal discharge FETs to
discharge the load when disabled. Upon turn-off these
internal switches on each output discharge the load
capacitance pulling the output to gnd. These switches are
also on when ENABLE is low thus an open slot is held at the
gnd level.
Recommended PCB Layout Design
To ensure accurate current sensing and control, the PCB
traces that connect each of the current sense resistors to the
ISL6111 must not carry any load current. This can be
accomplished by two dedicated PCB kelvin traces directly
from the sense resistors to the ISL6111, see examples of
correct and incorrect layouts below in Figure 2. To reduce
TABLE 1.
SUPPLY
NOMINAL CURRENT REGULATION LEVEL (10%)
FOR EACH SUPPLY
+3.3V I
CR
((100A x R
CRSET
)/8.54)/R
RSENSE
+5.0V I
CR
((100A x R
CRSET
)/12)/R
RSENSE
+12V I
CR
(100A x R
CRSET
)/0.7
-12V I
CR
(100A x R
CRSET
)/3.3
TABLE 2.
CRTIM, VALUE 0.022F 0.1F1F
Nominal CR Duration 3.3ms 15ms 150ms
Nominal CR Duration = 150k X TIM cap value.
ISL6111

ISL6111CRZA

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers W/ANNEAL 20LD MLFP 5X5 PCI HOTSWAP CNTR
Lifecycle:
New from this manufacturer.
Delivery:
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