UJA1078_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 43 of 53
NXP Semiconductors
UJA1078
High-speed CAN/dual LIN core system basis chip
[5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t
trig(wd)1
after the start of the watchdog
period (or in the first half of the watchdog period).
[6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Tab le 4
); valid in watchdog
Window mode only.
[7] The watchdog will be reset if it is in window mode and is triggered at least t
trig(wd)1
, but not more than t
trig(wd)2
, after the start of the
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 15. Timing test circuit for CAN transceiver
Fig 16. CAN transceiver timing diagram
SBC
BAT
CANL
CANH
TXDC
R
CANH
−
R
CANL
RXDC
C
RXDC
GND
C
CANH
− C
CANL
015aaa079
CANH
CANL
t
d(TXDC-busdom)
TXDC
V
O(dif)bus
RXDC
HIGH
HIGH
LOW
LOW
dominant
recessive
0.9 V
0.5 V
t
d(busdom-RXDC)
t
d(TXDC-busrec)
t
d(busrec-RXDC)
t
d(TXDCH-RXDCH)
t
d(TXDCL-RXDCL)
015aaa15