25AA640-I/SN Datasheet 25LC640XT-I/ST, 25AA640-I/P, 25LC640-I/SN | P10-P12

25AA640/25LC640

3.5 Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. The STATUS register

may be read at any time, even during a write cycle. The

STATUS register is formatted as follows:

The Write-In-Process (WIP) bit indicates whether the

25XX640 is busy with a write operation. When set to a

‘1’, a write is in progress, when set to a ‘0’, no write is

in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch. When set to a ‘1’, the latch

allows writes to the array and STATUS register, when

set to a ‘0’, the latch prohibits writes to the array and

STATUS register. The state of this bit can always be

updated via the WREN or WRDI commands regardless

of the state of write protection on the STATUS register.

This bit is read-only.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSR instruction. These

bits are nonvolatile.

See Figure 3-6 for RDSR timing sequence.

FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE

7 654 3 2 1 0

WPEN X X X BP1 BP0 WEL WIP

9101112131415

11000000

7654 210

Instruction

Data from STATUS Register

High-Impedance

SCK

0 23456718

25AA640/25LC640

3.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to select one of four levels of protection for the

array by writing to the appropriate bits in the STATUS

The user has the ability to write-protect none, one, two,

or all four of the segments of the array. The partitioning

is controlled as shown in Table 3-2.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP

pin. The

Write-Protect (WP

) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the pro-

grammable hardware write-protect feature. Hardware

write protection is enabled when the WP

pin is low and

the WPEN bit is high. Hardware write protection is dis-

abled when either the WP pin is high or the WPEN bit

is low. When the chip is hardware write-protected, only

writes to nonvolatile bits in the STATUS register are dis-

abled. See Table 3-3 for a matrix of functionality on the

WPEN bit.

See Figure 3-7 for WRSR timing sequence.

TABLE 3-2: ARRAY PROTECTION

FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE

BP1 BP0

Array Addresses

Write-Protected

00 none

01 upper 1/4

(1800h-1FFFh)

10 upper 1/2

(1000h-1FFFh)

11 all

(0000h-1FFFh)

9101112131415

0 1000000

7654

210

Instruction Data to STATUS Register

High-Impedance

SCK

0 2345671

25AA640/25LC640

3.7 Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write, or STATUS register

write, the write enable latch is reset

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

3.8 Power-On-State

The 25XX640 powers on in the following state:

• The device is in low-power Standby mode

(CS

= 1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low transition on CS

is required to enter

the active state

TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX

WPEN WP WEL Protected Blocks Unprotected Blocks STATUS Register

XX 0 Protected Protected Protected

0X 1 Protected Writable Writable

1 Low 1 Protected Writable Protected

X High 1 Protected Writable Writable

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

25AA640-I/SN

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EEPROM 8kx8 - 1.8V

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25AA640-I/SN

25AA640-I/SN

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