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BD35231HFN-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
BD3523HFN, BD35230HFN, BD35231HFN
Technical Note
16/20
www.rohm.com
2009.04 - Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
●Recommended Circuit Example (BD35230HFN/BD35231HFN)
Component
Recommended
Value
Programming Notes and Precautions
C3 22μF
To assure output voltage stability, please be certain the output capacitors are connected
between Vo pin and GND. Output capacitors play a role in loop gain phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature and
load conditions. Also, note that connecting different types of capacitors in series may result in
insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation across a variety of temperature and load conditions.
C1/C2 1μF/10μF
Input capacitors reduce the output impedance of the voltage supply source connected to the
(V
CC, VIN) input pins. If the impedance of this power supply were to increase, input voltage
(VCC, VIN) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 1μF/10μF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and the
substrate wiring pattern. In light of this information, please confirm operation across a variety
of temperature and load conditions.
C4 0.01μF
The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current
from going through the load (V
IN to VO) and impacting output capacitors at power supply
start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function
is deactivated. The temporary reference voltage is proportionate to time, due to the current
charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this
reference voltage. Capacitors with low susceptibility to temperature are recommended, in
order to assure a stable soft-start time.
C5 1000pF
This component is employed when the C16 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.
6
V
cc
EN
VIN
4
3
2
1
V
o
V
o
8
7
6
5
GND
FB
NRCS
C1
V
cc
R4
EN
C4
VIN
C2
C3
GND
FB
V
o
C5
BD3523HFN, BD35230HFN, BD35231HFN
Technical Note
17/20
www.rohm.com
2009.04 - Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
●Input-Output Equivalent Circuit Diagram (BD3523HFN)
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
400kΩ
EN
1kΩ
VIN
VIN
VIN
VIN
VIN
VIN
NRCS
VCC
1kΩ
1kΩ
1kΩ
90kΩ
210kΩ
1kΩ
VCC
1kΩ
1kΩ
VCC
Vo
Vo
50kΩ
10kΩ
1kΩ
Vo
Vo
Vo
Vo
VCC
FB
1kΩ
1kΩ
BD3523HFN, BD35230HFN, BD35231HFN
Technical Note
18/20
www.rohm.com
2009.04 - Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.
TSD on temperature [°C] (typ.)
BD3523HFN/BD35230HFN/BD35231HFN 175
10. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.
11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring
pattern of any external components, either.
Example of IC structure
Resistor Transistor (NPN)
N
N N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
P
aras
iti
c
element
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

BD35231HFN-TR

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LDO Voltage Regulators LDO REGULATOR POS 1.2V 2A 8PIN
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