© Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 8
1 Publication Order Number:
MUN5211T1/D
MUN5211T1 Series
Preferred Devices
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base-emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC-70/SOT-323 package which is designed for low power
surface mount applications.
Features
•Simplifies Circuit Design
•Reduces Board Space
•Reduces Component Count
•The SC-70/SOT-323 package can be soldered using wave or reflow.
The modified gull-winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
•Available in 8 mm embossed tape and reel. Use the Device Number
to order the 7 inch/3000 unit reel.
•Pb-Free Packages are Available
MAXIMUM RATINGS (T
A
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Collector-Base Voltage V
CBO
50 Vdc
Collector-Emitter Voltage V
CEO
50 Vdc
Collector Current I
C
100 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
P
D
202 (Note 1)
310 (Note 2)
1.6 (Note 1)
2.5 (Note 2)
mW
mW/°C
Thermal Resistance, Junction-to-Ambient
R
q
JA
618 (Note 1)
403 (Note 2)
°C/W
Thermal Resistance, Junction-to-Lead
R
q
JL
280 (Note 1)
332 (Note 2)
°C/W
Junction and Storage Temperature
Range
T
J
, T
stg
-55 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR-4 @ Minimum Pad.
2. FR-4 @ 1.0 x 1.0 inch Pad.
Preferred devices are recommended choices for future use
and best overall value.
NPN SILICON
BIAS RESISTOR
TRANSISTORS
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
PIN 1
BASE
(INPUT)
R
1
R
2
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
SC-70/SOT-323
CASE 419
STYLE 3
3
2
1
MARKING DIAGRAM
8x = Device Code
M = Date Code*
G = Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
8x
M G
G
