LTC1659CMS8#PBF

LTC1659
4
1659fa
ELECTRICAL CHARACTERISTICS
The denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
OUT
unloaded, REF ≤ V
CC
, T
A
= T
MIN
to T
MAX
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching (V
CC
= 4.5V to 5.5V
t
1
D
IN
Valid to CLK Setup
40 ns
t
2
D
IN
Valid to CLK Hold
0ns
t
3
CLK High Time (Note 7)
40 ns
t
4
CLK Low Time (Note 7)
40 ns
t
5
C
S/LD Pulse Width (Note 7)
50 ns
t
6
LSB CLK to
C
S/LD (Note 7)
40 ns
t
7
C
S/LD Low to CLK (Note 7)
20 ns
t
8
D
OUT
Output Delay C
LOAD
= 15pF
5150ns
t
9
CLK Low to
C
S/LD Low (Note 7)
20 ns
Switching (V
CC
= 2.7V to 5.5V)
t
1
D
IN
Valid to CLK Setup
60 ns
t
2
D
IN
Valid to CLK Hold
0ns
t
3
CLK High Time (Note 7)
60 ns
t
4
CLK Low Time (Note 7)
60 ns
t
5
C
S/LD Pulse Width (Note 7)
80 ns
t
6
LSB CLK to
C
S/LD (Note 7)
60 ns
t
7
C
S/LD Low to CLK (Note 7)
30 ns
t
8
D
OUT
Output Delay C
LOAD
= 15pF
10 220 ns
t
9
CLK Low to
C
S/LD Low (Note 7)
30 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity is defi ned from code 20 to code 4095 (full scale). See
Applications Information.
Note 3: Load is 5kΩ in parallel with 100pF.
Note 4: DAC switched between all 1s and the code corresponding to V
OS
for the part.
Note 5: Digital inputs at 0V or V
CC
.
Note 6: V
OUT
can only swing from (GND + |V
OS
|) to (V
CC
– |V
OS
|) when
output is unloaded.
Note 7: Guaranteed by design, not subject to test.
LTC1659
5
1659fa
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Minimum Output Voltage vs
Output Sink Current
Supply Headroom for Full Output
Swing vs Load Current
Supply Current vs
Logic Input Voltage
Supply Current vs Temperature
CODE
0 512 1824 1536 2048 2560 3072 3584 4095
INL ERROR (LSB)
1659 • G01
5
4
3
2
1
0
–1
–2
–3
–4
–5
CODE
0
DNL ERROR (LSB)
0.5
0
0.5
1024 2048 2560
1659 • G02
512 1536 3072 3584
4095
OUTPUT SINK CURRENT (mA)
0 5 10 15
OUTPUT PULL-DOWN VOLTAGE (V)
1659 • G03
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25°C
–55°C
125°C
CODE = ALL ZEROS
V
CC
= 5V
LOAD CURRENT (mA)
0 5 10 15
V
CC
– V
OUT
(V)
1659 • G04
0.6
0.5
0.4
0.3
0.2
0.1
0
ΔV
OUT
< 1 LSB
CODE = ALL 1s
V
OUT
= 4.095V
25°C
–55°C
125°C
LOGIC INPUT VOLTAGE (V)
012345
SUPPLY CURRENT (mA)
1659 • G05
2
1.6
1.2
0.8
0.4
0
V
CC
= 5V
TEMPERATURE (C)
–55 –35 –15 5 25 45 65 85 105 125
SUPPLY CURRENT (μA)
1659 • G06
300
290
280
270
260
250
240
230
220
V
CC
= 5.5V
V
CC
= 5.0V
V
CC
= 4.5V
LTC1659
6
1659fa
PIN FUNCTIONS
BLOCK DIAGRAM
CLK (Pin 1): Serial Interface Clock. Internal Schmitt trigger
on this input allows direct optocoupler interface.
D
IN
(Pin 2): Serial Interface Data. Data on the D
IN
pin is
latched into the shift register on the rising edge of the
serial clock.
C
S/LD (Pin 3): Serial Interface Enable and Load Control.
When
C
S/LD is low the CLK signal is enabled, so the data
can be clocked in. When
C
S/LD is pulled high, data is loaded
from the shift register into the DAC register, updating the
DAC output and the CLK is disabled internally.
D
OUT
(Pin 4): Output of the Shift Register which Becomes
Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
REF (Pin 6): Reference Input. This pin can be tied to V
CC
.
The output will swing from 0V to REF. The typical input
resistance is 28k.
V
OUT
(Pin 7): Buffered DAC Output.
V
CC
(Pin 8): Positive Supply Input. 2.7V ≤ V
CC
≤ 5.5V.
Requires a bypass capacitor to ground.
DAC
REGISTER
LD
12-BIT
SHIFT
REGISTER
POWER-ON
RESET
1659 BD
CLK
1
D
IN
2
D
OUT
4
V
OUT
7
REF
6
GND
5
V
CC
8
3
CS/LD
12-BIT
DAC
+

LTC1659CMS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Single 12-Bit Vout DAC
Lifecycle:
New from this manufacturer.
Delivery:
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