1/10September 2003
■ MEETS OR EXCEEDS THE
REQUIREMENTS OF ANSI TIA/EIA-644
STANDARD
■ OPERATES WITH A SINGLE 3.3V SUPPLY
■ DESIGNED FOR SIGNALING RATE UP TO
400Mbps
■ DIFFERENTIAL INPUT THRESHOLDS
±100mV MAX
■ TYPICAL PROPAGATION DELAY TIME OF
2.5ns
■ POWER DISSIPATION 60mW TYPICAL PER
RECEIVER AT 200MHz
■ LOW VOLATGE TTL (LVTTL) LOGIC
OUTPUT LEVELS
■ OPEN CIRCUIT FAIL SAFE
■ ESD PROTECTION:
7KV RECEIVER PINS
3KV ALL PINS VS GND
DESCRIPTION
The STLVDS9637, is a differential line receiver
that implements the electrical characteristics of
low voltage differential signaling (LVDS). This
signaling technique lowers the output voltage
levels of 5V differential standard levels (such as
TIA/EIA-422B) to reduce the power, increase the
switching speeds and allow operations with a 3.3V
supply rail. This differential receiver provides a
valid logical output state with a 3.3V supply rail. It
also provides a valid logical output state with a
±100mV differential input voltage within the input
common mode voltage range. The input common
mode voltage allows 1V of ground potential
difference between two LVDS nodes.
The intended application of this device and
signalling technique is both point-to-point and
multidrop data transmission over controlled
impedance media approximately 100Ω.The
transmission media may be printed circuit board
traces, backplanes or cables. The ultimate rate
and distance of data transfer depend upon the
attenuation characteristics of the media and noise
coupling to the environment.
The STLVDS9637 version is characterized for
operation from -40°C to 85°C.
ORDERING CODES
Type
Temperature
Range
Package Comments
STLVDS9637BD -40 to 85 °C SO-8 (Tube) 100parts per tube / 40tube per box
STLVDS9637BDR -40 to 85 °C SO-8 (Tape & Reel) 2500 parts per reel
STLVDS9637
HIGH SPEED
DIFFERENTIAL LINE RECEIVERS
SOP
Obsolete Product(s) - Obsolete Product(s)