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X40626V14-4.5A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
13
FN8119.0
March 28, 2005
Figure 14. Sequential Read Sequence
X40626 Addressing
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array
– one bit of ‘0’.
– next two bits are the device address. (S1 and S0)
– one bit of the slave command byte is a R/W
bit. The
R/W
bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W
bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is 00H on a power-up condition.
The master must supply the two word address byte as
shown in Figure 15.
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
S
1
S
0
X40626
14
FN8119.0
March 28, 2005
Figure 15. X40626 Addressing
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is in the input mode.
– RESET
Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
– Communication to the device is inhibited while
RESET
is active and any in-progress communica-
tion is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
Symbol Table
R/WS0S10101
Slave Address Byte
Device Identifier Device Select
A8A9A10A11A12
A13A14A15
Word Address Byte 1
High Order Word Address
A0A1A2
Word Address Byte 0
Low Order Word Address
A3
A4A5A6A7
D0D1D2D3D4D5D6D7
Data Byte
0
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X40626
15
FN8119.0
March 28, 2005
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current (sink) ...................................10mA
Lead temperature (soldering, 10 seconds)........ 300°C
Table 2. Recommended Operating Conditions
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) The device enters the Active state after any start, and remains active until: (a) 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; or (b) 200nS after a stop ending a read operation.
(2) The device enters the Active state after any start, and remains active until t
WC
after a stop ending a write operation.
(3) The device goes into Standby: (a) 200nS after any stop, except those that initiate a nonvolatile write cycle; or (b) t
WC
after a stop that
initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.
Temp Min. Max.
Commercial 0°C 70°C
Industrial -40°C +85°C
Symbol Parameter
V
CC
= 2.7 to 5.5V
Unit Test ConditionsMin Max
I
CC1
(1)
Active Supply Current Read 1.0 mA V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9
f
SCL
= 400kHz, SDA = Open
I
CC2
(2)
Active Supply Current Write 3.0 mA
I
SB1
(2)
Standby Current DC (WDT off) 1 µAV
SDA
=V
SCL
=V
CC
Others=GND or V
CC
I
SB2
(3)
Standby Current DC (WDT on) 30 µAV
SDA
=V
SCL
=V
CC
Others=GND or V
CC
I
LI
Input Leakage Current 10 µAV
IN
= GND to V
CC
I
LO
Output Leakage Current 10 µAV
SDA
= GND to V
CC
Device is in Standby
V
IL
Input LOW Voltage -1 V
CC
x 0.3 V
V
IH
Input HIGH Voltage V
CC
x 0.7 V
CC
+0.5 V
V
HYS
Schmitt Trigger Input Hysteresis
Fixed input level
V
CC
related level
0.2
.05 x V
CC
V
V
V
OL
Output LOW Voltage 0.4 V I
OL
= 1.0mA (V
CC
=3V)
I
OL
= 3.0mA (V
CC
=5V)
X40626
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

X40626V14-4.5A

Mfr. #:
Buy X40626V14-4.5A
Manufacturer:
Renesas / Intersil
Description:
IC SUPERVISOR CPU DUAL 14-TSSOP
Lifecycle:
New from this manufacturer.
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