R5F21217KFP#U1 Datasheet R5F21217JFP, R5F21216JFP, R5F2121CJFP#U0 | P28-P30

R8C/20 Group, R8C/21 Group 5. Electrical Characteristics

Rev.2.00 Aug 27, 2008 Page 26 of 41

REJ03B0120-0200

NOTES:

1. Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.

2. This condition (the minimum value of external power V

CC rise gradient) does not apply if Vpor2 ≥ 1.0 V.

3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the

VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.

4. t

w(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on

reset. When turning on the power for the first time, maintain tw(por1) for 30s or more if -20°C ≤ Topr ≤ 125°C, maintain t

w(por1)

for 3,000s or more if -40°C ≤ Topr < -20°C.

Figure 5.3 Power-on Reset Circuit Electrical Characteristics

Table 5.8 Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics

(3)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

por1

Power-on reset valid voltage

(4)

−−0.1 V

por2 Power-on reset or voltage monitor 1 valid voltage 0 − Vdet1 V

trth External power V

CC rise gradient VCC ≤ 3.6 V

(2)

−−mV/msec

CC > 3.6 V

(2)

− 2,000 mV/msec

× 32

fOCO-S

Vdet1

(3)

Vpor1

tw(por1)

Vdet1

(3)

Vpor2

2.0 V

trth

External power Vcc

Internal reset signal

(“L” valid)

Sampling time

(1, 2)

td(Vdet1-A)

× 32

fOCO-S

NOTES:

1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.

2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.

3. V

det1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of

Hardware Manual for details.

R8C/20 Group, R8C/21 Group 5. Electrical Characteristics

Rev.2.00 Aug 27, 2008 Page 27 of 41

REJ03B0120-0200

NOTES:

1. V

CC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.

2. The standard value shows when the reset is deasserted for the FRA1 register.

NOTE:

1. V

CC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.

NOTES:

1. The measurement condition is V

CC = 2.7 to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless

otherwise specified.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

3. Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode.

Table 5.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition

Standard

Unit

Min. Typ. Max.

fOCO40M High-speed on-chip oscillator frequency temperature

• supply voltage dependence

CC = 4.75 V to 5.25 V,

0°C ≤ Topr ≤ 60°C

(2)

39.2 40 40.8 MHz

CC = 3.0 V to 5.25 V,

-20°C ≤ Topr ≤ 85°C

(2)

38.8 40 41.2 MHz

CC = 3.0 V to 5.5 V,

-40°C ≤ Topr ≤ 85°C

(2)

38.4 40 41.6 MHz

CC = 3.0 V to 5.5 V,

-40°C ≤ Topr ≤ 125°C

(2)

38.0 40 42.0 MHz

CC = 2.7 V to 5.5 V,

-40°C ≤ Topr ≤ 125°C

(2)

37.6 40 42.4 MHz

− The value of the FRA1 register when the reset is

deasserted

08h 40 F7h −

− High-speed on-chip oscillator adjustment range Adjust the FRA1 register to

-1 bit (the value when the

reset is deasserted)

− + 0.3 − MHz

− Oscillation stability time − 10 100 µs

− Self power consumption when high-speed on-chip

oscillator oscillating

CC = 5.0 V, Topr = 25°C − 600 −µA

Table 5.10 Low-Speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition

Standard

Unit

Min. Typ. Max.

fOCO-S Low-speed on-chip oscillator frequency 40 125 250 kHz

− Oscillation stability time − 10 100 µs

− Self power consumption when low-speed on-chip

oscillator oscillating

CC = 5.0 V, Topr = 25°C − 15 −µA

Table 5.11 Power Supply Circuit Timing Characteristics

Symbol Parameter Condition

Standard

Unit

Min. Typ. Max.

d(P-R) Time for internal power supply stabilization during

power-on

(2)

1 − 2000 µs

d(R-S)

STOP exit time

(3)

−−150 µs

R8C/20 Group, R8C/21 Group 5. Electrical Characteristics

Rev.2.00 Aug 27, 2008 Page 28 of 41

REJ03B0120-0200

NOTES:

1. V

CC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. 1t

CYC = 1/f1(s)

Table 5.12 Timing Requirements of Clock Synchronous Serial I/O with Chip Select

(1)

Symbol Parameter Conditions

Standard

Unit

Min. Typ. Max.

SUCYC SSCK clock cycle time 4 −−

CYC

(2)

tHI SSCK clock “H” width 0.4 − 0.6 tSUCYC

tLO SSCK clock “L” width 0.4 − 0.6 tSUCYC

tRISE SSCK clock rising time Master −− 1

CYC

(2)

Slave −− 1 µs

FALL SSCK clock falling time Master −− 1

CYC

(2)

Slave −− 1 µs

SU SSO, SSI data input setup time 100 −−ns

H SSO, SSI data input hold time 1 −−

CYC

(2)

tLEAD

SCS setup time

Slave 1t

CYC + 50 −−ns

LAG

SCS hold time

Slave 1t

CYC + 50 −−ns

OD SSO, SSI data output delay time −− 1

CYC

(2)

tSA SSI slave access time −−1tCYC + 100 ns

OR SSI slave out open time −−1tCYC + 100 ns

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R5F21217KFP#U1

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16-bit Microcontrollers - MCU MCU 3/5V 48+2K -40/125C AU PbFree 48LQFP

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