10
AT25HP256/512
1113I–SEEPR–6/03
READ SEQUENCE (READ): Reading the AT25HP256/512 via the SO (Serial Output)
pin requires the following sequence. After the CS
line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed by the byte address to be read
(Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data
(D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is
to be read, the CS
line should be driven high after the data comes out. The READ
sequence can be continued since the byte address is automatically incremented and
data will continue to be shifted out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the entire memory to be read in one
continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25HP256/512, two separate
instructions must be executed. First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also,
the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the Block Write Protection Level. During an internal
write cycle, all commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS
line is pulled low to
select the device, the WRITE op-code is transmitted via the SI line followed by the byte
address and the data (D7-D0) to be programmed (Refer to Table 6). Programming will
start after the CS
pin is brought high. (The LOW to High transition of the CS pin must
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STA-
TUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If
Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction
is enabled during the WRITE programming cycle.
The AT25HP256/512 is capable of a 128-byte PAGE WRITE operation. After each byte
of data is received, the seven low order address bits are internally incremented by one;
the high order bits of the address will remain constant. If more than 128-bytes of data
are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25HP256/512 is automatically returned to the write disable state at
the completion of a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS
is brought high. A new CS fall-
ing edge is required to re-initiate the serial communication.
NOTE: 128-byte PAGE WRITE operation only
. Content of the page in the array will not
be guaranteed if less than 128 bytes of data is received (byte write is not supported).
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
Table 6. Address Key
Address AT25HP256/512
A
N
A
14
- A
0
/ A
15
- A
0
Don’t Care Bits A
15
/ none
Table 5. WPEN Operation
WPEN WP WEN ProtectedBlocks UnprotectedBlocks Status Register
