LT8614
10
8614fc
For more information www.linear.com/LT8614
BLOCK DIAGRAM
+
+
+
SLOPE COMP
INTERNAL 0.97V REF
OSCILLATOR
200kHz TO 3MHz
BURST
DETECT
3.4V
REG
M1
M2
C
BST
C
OUT
V
OUT
8614 BD
SW
L
BST
8, 9, 21, 22
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
ERROR
AMP
SHDN
±9%
V
C
SHDN
TSD
INTV
CC
UVLO
V
IN
UVLO
SHDN
TSD
V
IN
UVLO
EN/UV
1V
+
14
4
3
18
GND
INTV
CC
2
BIAS
1
V
IN2
13
GND1
6, 7
GND2
10, 11
PG
19
FB
R1C1
R3
OPT
R4
OPT
R2
R
T
C
SS
OPT
V
OUT
20
TR/SS
2.2µA
16
RT
15
SYNC/MODE
17
V
IN1
V
IN
C
IN1
C
IN3
C
VCC
C
IN2
PIN FUNCTIONS
SYNC/MODE (Pin 17): External Clock Synchronization
Input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to a clock source for synchroniza
-
tion to an external frequency. Apply a DC voltage of 3V or
higher or tie to INTV
CC
for pulse-skipping mode. When
in pulse-skipping mode, the I
Q
will increase to several
hundred µA. Do not float this pin.
GND (Pins 18): LT8614 Ground Pin. Connect this pin to
system ground and to the ground plane.
PG (Pin 19): The PG pin is the open-drain output of an
internal comparator. PG remains low until the FB pin is
within ±9% of the final regulation voltage, and there are
no fault conditions. PG is valid when V
IN
is above 3.4V,
regardless of EN/UV pin state.
FB (Pin 20): The LT8614 regulates the FB pin to 0.970V.
Connect the feedback resistor divider tap to this pin. Also,
connect a phase lead capacitor between FB and V
OUT
.
Typically, this capacitor is 4.7pF to 22pF.
SW (Exposed Pad Pins 21, 22): The exposed pads should
to connected and soldered to the SW trace for good thermal
performance. If necessary due to manufacturing limita
-
tions Pins 21 and 22 may be
left disconnected, however
thermal performance will be degraded.
LT8614
11
8614fc
For more information www.linear.com/LT8614
OPERATION
The LT8614 is a monolithic, constant frequency, current
mode step-down DC/DC converter. An oscillator, with
frequency set using a resistor on the RT pin, turns on
the internal top power switch at the beginning of each
clock cycle. Current in the inductor then increases until
the top switch current comparator trips and turns off the
top power switch. The peak inductor current at which
the top switch turns off is controlled by the voltage on
the internal VC node. The error amplifier servos the VC
node by comparing the voltage on the V
FB
pin with an
internal 0.97V reference. When the load current increases
it causes a reduction in the feedback voltage relative to
the reference leading the error amplifier to raise the VC
voltage until the average inductor current matches the new
load current. When the top power switch turns off, the
synchronous power switch turns on until the next clock
cycle begins or inductor current falls to zero. If overload
conditions result in more than 6.9A flowing through the
bottom switch, the next clock cycle will be delayed until
switch current returns to a safe level.
If the EN/UV pin is low, the
LT8614 is shut down and
draws
A from the input. When the EN/UV pin is above
1V, the switching regulator will become active.
To optimize efficiency at light loads, the LT8614 operates
in Burst Mode operation in light load situations. Between
bursts, all circuitry associated with controlling the output
switch is shut down, reducing the input supply current to
1.7μA. In a typical application, 2.5μA will be consumed
from the input supply when regulating with no load. The
SYNC pin is tied low to use Burst Mode operation and can
be tied to a logic high to use pulse-skipping mode. If a
clock is applied to the SYNC pin the part will synchronize to
an external clock frequency and operate in pulse-skipping
mode. While in pulse-skipping mode the oscillator operates
continuously and positive SW transitions are aligned to
the clock. During light loads, switch pulses are skipped
to regulate the output and the quiescent current will be
several hundred µA.
To improve efficiency across all loads, supply current to
internal circuitry can be sourced from the BIAS pin when
biased at 3.3V or above. Else, the internal circuitry will draw
current from V
IN
. The BIAS pin should be connected to
V
OUT
if the LT8614 output is programmed at 3.3V or above.
Comparators monitoring the FB pin voltage will pull the
PG pin low if the output voltage varies more than ±9%
(typical) from the set point, or if a fault condition is present.
The oscillator reduces the LT8614’s operating frequency
when the voltage at the FB pin is low. This frequency
foldback helps to control the inductor current when the
output voltage is lower than the programmed value which
occurs during start-up or overcurrent conditions. When
a clock is applied to the SYNC pin or the SYNC pin is
held DC high, the frequency foldback is disabled and the
switching frequency will slow down only during overcur
-
rent conditions.
LT8614
12
8614fc
For more information www.linear.com/LT8614
APPLICATIONS INFORMATION
Low EMI PCB Layout
The LT8614 is specifically designed to minimize EMI/EMC
emissions and also to maximize efficiency when switching
at high frequencies. For optimal performance the LT8614
requires the use of multiple V
IN
bypass capacitors.
Tw o smallF capacitors should be placed as close as
possible to the LT8614: One capacitor should be tied to
V
IN1
/GND1; a second capacitor should be tied to V
IN2
/
GND2. A third capacitor with a larger value, 2.2µF or
higher, should be placed near V
IN1
or V
IN2
.
See Figure 1 for a recommended PCB layout.
For more detail and PCB design files refer to the Demo
Board guide for the LT8614.
Note that large, switched currents flow in the LT8614
V
IN1
, V
IN2
, GND1, and GND2 pins and the input capacitors
(C
IN1
, C
IN2
). The loops formed by the input capacitors
should be as small as possible by placing the capacitors
adjacent to the V
IN1/2
and GND1/2 pins. Capacitors with
small case size such as 0603 are optimal due to lowest
parasitic inductance.
The input capacitors, along with the inductor and output
capacitors, should be placed on the same side of
the
circuit
board, and their connections should be made on
that layer. Place a local, unbroken ground plane under the
application circuit on the layer closest to the surface layer.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and RT nodes small so that the ground
Figure 1. Recommended PCB Layout for the LT8614
V
V
V
V
V
V
1
6
11
16
GROUND PLANE
ON LAYER 2
20
R1
R2
C
VCC
C
BST
C
IN1
C
IN2
C
IN3
C
OUT
L
R
T
C
SS
C1 R
PG
17
7 10
22
21
GROUND VIA V
IN
VIA V
OUT
VIA OTHER SIGNAL VIAS
9614 F01
V

LT8614EUDC#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 42V, 4A Synchronous Step-Down SILENT SWITCHER with 2.5 A Quiescent Current
Lifecycle:
New from this manufacturer.
Delivery:
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