MAX3880ECB+TD Datasheet MAX3880ECB+D, MAX3880ECB+TD | P7-P9

MAX3880

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

_______________________________________________________________________________________ 7

dropped, shifting the alignment between PCLK and

data by 1 bit. The SYNC signal must be at least four

serial bit periods wide (4 x 402ps). See Figure 4 for the

timing diagram and Figure 5 for the timing parameters

diagram.

Input Amplifier

The input amplifiers on both the main data and system

loopback accept a differential input amplitude from

50mVp-p to 800mVp-p. The bit error rate (BER) is bet-

ter than 1 x 10

-10

for input signals as small as 9.5mVp-

p, although the jitter tolerance performance will be

degraded. For interfacing with PECL signal levels, see

Applications Information.

Phase Detector

The phase detector in the MAX3880 produces a volt-

age proportional to the phase difference between the

incoming data and the internal clock. Because of its

feedback nature, the PLL drives the error voltage to

zero, aligning the recovered clock to the center of the

incoming data eye for retiming. The external phase

adjust pins (PHADJ+, PHADJ-) allow the user to vary

the internal phase alignment.

Frequency Detector

The digital frequency detector (FD) aids frequency

acquisition during start-up conditions. The frequency

difference between the received data and the VCO

clock is derived by sampling the in-phase and quadra-

ture VCO outputs on both edges of the data input sig-

nal. Depending on the polarity of the frequency

difference, the FD drives the VCO until the frequency

difference is reduced to zero. Once frequency acquisi-

tion is complete, the FD returns to a neutral state. False

locking is completely eliminated by this digital frequen-

cy detector.

Loop Filter and VCO

The phase detector and frequency detector outputs are

summed into the loop filter. A 1.0µF capacitor, C

, is

required to set the PLL damping ratio.

The loop filter output controls the on-chip LC VCO run-

ning at 2.488GHz. The VCO provides low phase noise

and is trimmed to the correct frequency.

Loss-of-Lock Monitor

A loss-of-lock (LOL) monitor is included in the

MAX3880 frequency detector. A loss-of-lock condition

is signaled immediately with a TTL low. When the PLL is

frequency-locked, LOL switches to TTL high in approxi-

mately 800ns.

Note that the LOL monitor is only valid when a data

stream is present on the inputs to the MAX3880. As a

result, LOL does not detect a loss-of-power condition

resulting from a loss of the incoming signal.

SDI

SYNC

PCLK

D15 D14 D13

D16 D32 D48

1 BIT HAS SLIPPED

IN THIS TIME SLICE

D65

(LSB) PD0

D1 D17 D33 D49 D66

PD1

D15

(MSB)

TRANSMITTED FIRST

D31 D47 D64 D80

PD15

•

Figure 4. Timing Diagram

MAX3880

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

8 _______________________________________________________________________________________

Low-Voltage Differential-Signal (LVDS)

Inputs and Outputs

The MAX3880 features LVDS inputs and outputs for

interfacing with high-speed digital circuitry. The LVDS

standard is based on the IEEE 1596.3 LVDS specifica-

tion. This technology uses 500mVp-p to 800mVp-p dif-

ferential low-voltage swings to achieve fast transition

times, minimize power dissipation, and improve noise

immunity. For proper operation, the parallel clock and

data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-)

require 100Ω differential DC termination between the

positive and negative outputs. Do not terminate these

outputs to ground. The synchronization LVDS inputs

(SYNC+, SYNC-) are internally terminated with 100Ω

differential input resistance and therefore do not require

external termination.

Design Procedure

Jitter Tolerance and Input

Sensitivity Trade-Offs

When the received data amplitude is higher than

50mVp-p, the MAX3880 provides a typical jitter toler-

ance of 0.46 UI at jitter frequencies greater than

10MHz. The SDH/SONET jitter tolerance specification is

0.15UI, leaving a jitter allowance of 0.31UI for receiver

preamplifier and postamplifier design.

The BER is better than 1 x 10

-10

for input signals

greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will

be degraded, but will still be above the SDH/SONET

requirement. Trade-offs can be made between jitter tol-

erance and input sensitivity according to the specific

application. See the Typical Operating Characteristics

for Jitter Tolerance and BER vs. Input Voltage graphs.

Applications Information

Consecutive Identical Digits (CIDs)

The MAX3880 has a low phase and frequency drift in

the absence of data transitions. As a result, long runs of

consecutive zeros and ones can be tolerated while

maintaining a BER of 1 x 10

-10

. The CID tolerance is

tested using a 2

- 1 pseudorandom bit stream

(PRBS), substituting a long run of zeros to simulate the

worst case. A CID tolerance of greater than 2,000 bits

is typical.

Phase Adjust

The internal clock is aligned to the center of the data

eye. For specific applications, this sampling position

can be shifted using the PHADJ inputs to optimize BER

performance. The PHADJ inputs operate with differen-

tial input voltages up to ±1.5V. A simple resistor-divider

with a bypass capacitor is sufficient to set these levels

(Figure 6). When the PHADJ inputs are not used, they

should be tied directly to V

System Loopback

The MAX3880 is designed to allow system loopback

testing. The user can connect a serializer output

(MAX3890) in a transceiver directly to the SLBI+ and

SLBI- inputs of the MAX3880 for system diagnostics. To

select the SLBI± inputs, apply a TTL logic high to the

SIS pin.

PCLK

PD0–PD15

NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-).

CLK-Q

Figure 5. Timing Parameters

MAX3880

PHADJ+ (PIN 5)

PHADJ- (PIN 6)

3.3V

Figure 6. Phase-Adjust Resistor-Divider

MAX3880

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

_______________________________________________________________________________________ 9

Interfacing with PECL Input Levels

When interfacing with differential PECL input levels, it is

important to attenuate the signal while still maintaining

50Ω termination (Figure 7). AC-coupling is also

required to maintain the input common-mode level.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies, keep ground con-

nections short, and use multiple vias where possible.

Use controlled impedance transmission lines to inter-

face with the MAX3880 high-speed inputs and outputs.

Power-supply decoupling should be placed as close to

as possible. To reduce feedthrough, take care to

isolate the input signals from the output signals.

MAX3880

50Ω

100Ω

PECL

LEVELS

SDI+

25Ω

0.1µF

SDI-

Figure 7. Interfacing with PECL Input Levels

Chip Information

TRANSISTOR COUNT: 4102

P1-P3 P4-P6 P7-P9 P10-P12

MAX3880ECB+TD

Mfr. #:

Buy MAX3880ECB+TD

Manufacturer:

Maxim Integrated

Description:

IC DESERIALIZER 2.488GBPS 64TQFP

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MAX3880ECB+TD

MAX3880ECB+TD

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