74F169SJX

© 2000 Fairchild Semiconductor Corporation DS009488 www.fairchildsemi.com
April 1988
Revised September 2000
74F169 4-Stage Synchronous Bidirectional Counter
74F169
4-Stage Synchronous Bidirectional Counter
General Description
The 74F169 is a fully synchronous 4-stage up/down
counter. The 74F169 is a modulo-16 binary counter. Fea-
tures a preset capability for programmable operation, carry
lookahead for easy cascading and a U/D
input to control
the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the
LOW-to-HIGH transition of the clock.
Features
Asynchronous counting and loading
Built-in lookahead carry capability
Presettable for programmable operation
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F169SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F169SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F169PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F169
Unit Loading/Fan Out
Functional Description
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE
is LOW,
the data on the P
0
P
3
inputs enters the flip-flops on the
next rising edge of the clock. In order for counting to occur,
both CEP
and CET must be LOW and PE must be HIGH;
the U/D
input then determines the direction of counting.
The Terminal Count (TC
) output is normally HIGH and goes
LOW, provided that CET
is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC
output state is not a
function of the Count Enable Parallel (CEP
) input level.
Since the TC
signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC
. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
1. Count Enable
= CEP CET PE
2. Up: (74F169): TC = Q
0
Q
1
Q
2
Q
3
(Up) CET
3. Down: TC = Q
0
Q
1
Q
2
Q
3
(Down) CET
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
State Diagram
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
CEP Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
CET
Count Enable Trickle Input (Active LOW) 1.0/2.0 20 µA/1.2 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20
µA/0.6 mA
P
0
P
3
Parallel Data Inputs 1.0/1.0 20 µA/0.6 mA
PE
Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
U/D
Up-Down Count Control Input 1.0/1.0 20 µA/0.6 mA
Q
0
Q
3
Flip-Flop Outputs 50/33.3 1 mA/20 mA
TC
Terminal Count Output (Active LOW) 50/33.3 1 mA/20 mA
PE CEP CET U/D
Action on Rising
Clock Edge
L X X X Load (P
n
Q
n
)
H L L H Count Up (Increment)
H L L L Count Down (Decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
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74F169
Logic Diagram
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

74F169SJX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Counter Shift Registers 4-State Sy Bidir Ctr
Lifecycle:
New from this manufacturer.
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