AD712
Rev. H | Page 12 of 20
OP AMP SETTLING TIME—A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/µs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under 1 µs,
while retaining the ability to drive a 250 pF load capacitance
when operating as a unity-gain follower.
If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of ω
O
/2π, then Equation 1 accurately
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.
1
)(
2
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
ω
+
ω
−
=
sRC
G
s
CR
R
I
V
f
O
N
O
X
IN
O
(1)
Where
π
2
O
= unity-gain frequency of the op amp.
G
N
= noise gain of circuit
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
O
R
R
1
.
This equation can then be solved for C
f
()
2
1
2
O
N
O
X
O
N
X
R
GRC
R
G
C
ω
−+ω
+
ω
−
=
(2)
In these equations, Capacitance C
X
is the total capacitance
appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
circuit shown in Figure 32 can be used directly; Capacitance C
X
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).
V
OUT
R
L
C
L
C
F
R
I
O
R
O
C
X
1/2
AD712
+
–
00823-032
Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
When R
O
and I
O
are replaced with their Thevenin V
IN
and R
IN
equivalents, the general-purpose inverting amplifier shown in
Figure 33 is created. Note that when using this general model,
Capacitance C
X
is either the input capacitance of the op amp, if
a simple inverting op amp is being simulated, or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
V
OUT
R
L
C
L
C
F
R
V
IN
R
IN
C
X
1/2
AD712
+
–
00823-033
Figure 33. Simplified Model of the AD712 Used as an Inverter
In either case, Capacitance C
X
causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of C
X
can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor
(C
F
) to cancel the input pole and optimize amplifier response.
Figure 34 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
C
F
C
X
40
30
0
100
20
10
50
60
G
N
= 4.0
G
N
= 3.0
20 30 40 50
60
G
N
= 2.0
G
N
= 1.5
G
N
= 1.0
00823-034
Figure 34. Value of Capacitor C
F
vs. Value of C
X
