AD8367
Rev. A | Page 12 of 24
02710-029
50Ω
V
OUT
V
B1
V
B2
FROM
INTEGRATOR
Figure 29. A 50 Ω resistor is added to the
output to prevent package resonance.
POWER AND VOLTAGE METRICS
Although power is the traditional metric used in the analysis
of cascaded systems, most active circuit blocks fundamentally
respond to voltage. The relationship between power and voltage
is defined by the impedance level. When input and output
impedance levels are the same, power gain and voltage gain
are identical. However, when impedance levels change between
input and output, they differ. Thus, one must be very careful to
use the appropriate gain for system chain analyses. Quantities
such as OIP3 are quoted in dBV rms as well as dBm referenced
to 200 Ω. The dBV rms unit is defined as decibels relative to
1 V rms. In a 200 Ω environment, the conversion from dBV rms
to dBm requires the addition of 7 dB to the dBV rms value. For
example, a 2 dBV rms level corresponds to 9 dBm.
NOISE AND DISTORTION
Since the AD8367 consists of a passive variable attenuator
followed by a fixed gain amplifier, the noise and distortion
characteristics as a function of the gain voltage are easily
predicted. The input-referred noise increases in proportion to
the attenuation level.
Figure 30 shows noise figure, NF, as a
function of V
GAIN
for the MODE pin pulled high. The minimum
NF of 7.5 dB occurs at maximum gain and increases 1 dB for
every 1 dB reduction in gain. In receiver applications, the
minimum NF should occur at the maximum gain where the
received signal presumably is weak. At higher levels, a lower
gain is needed, and the increased NF becomes less important.
The input-referred distortion varies in a similar manner to the
noise.
Figure 30 illustrates how the third-order intercept point
at the input, IIP3, behaves as a function of V
GAIN
. The highest
IIP3 of 20 dBV rms (27 dBm re 200 Ω) occurs at minimum
gain. The IIP3 then decreases 1 dB for every 1 dB increase in
gain. At lower levels, a degraded IIP3 is acceptable. Overall, the
dynamic range, represented by the difference between IIP3 and
NF, remains reasonably constant as a function of gain. The
output distortion and compression are essentially independent
of the gain. At low gains, when the input level is high, input
overload can occur, causing premature distortion.
60
–30
–20
–10
00
10
20
30
40
50
60
–30
–20
–10
10
20
30
40
50
0 1.00.90.80.70.60.50.40.30.20.1
02710-030
V
GAIN
(V)
IIP3 (dBV)
NF (dB)
NF
IIP3
Figure 30. Noise Figure and Input Third-Order Intercept vs.
Gain (R
SOURCE
= 200 Ω)
OUTPUT CENTERING
To maximize the ac swing at the output of the AD8367, the
output level is centered midway between ground and the supply.
This is achieved when the DECL pin is bypassed to ground via a
shunt capacitor. The loop acts to suppress deviations from the
reference at outputs below its corner frequency while not affect-
ing signals above it, as shown in
Figure 31. The maximum
corner frequency with no external capacitor is 500 kHz. The
corner frequency can be lowered arbitrarily by adding an
external capacitor, C
HP
:
0.02(nF)
10
(kHz)
+
=
HP
HP
C
f
(3)
A 100 Ω in series with the C
HP
capacitor is recommended to
de-Q the resonant tank that is formed by the bond-wire
inductance and C
HP
. Failure to insert this capacitor can
potentially cause oscillations at higher frequencies at high
gain settings.
02710-031
MAIN
AMPLIFIER
g
m
VOUT
FROM
INPUT
HPFL
C
HP
R
HP
V
MID
DECL
A
V
= 1
Figure 31. The dc output level is centered to midsupply by a control loop
whose corner frequency is determined by C
HP
.
AD8367
Rev. A | Page 13 of 24
RMS DETECTION
The AD8367 contains a square-law detector that senses
the output signal and compares it to a calibrated setpoint of
354 mV rms, which corresponds to a 1 V p-p sine wave. This
setpoint is internally set and cannot be modified to change the
AGC setpoint and the resulting VOUT level without using
additional external components. This is described in the
Modifying the AGC Setpoint section.
Any difference between the output and setpoint generates
a current that is integrated by an external capacitor, C
AGC
,
connected from the DETO pin to ground, to provide an AGC
control voltage. There is also an internal 5 pF capacitor on the
DETO pin.
The resulting voltage is used as an AGC bias. For this
application, the MODE pin is pulled low and the DETO pin is
tied to the GAIN pin. The output signal level is then regulated
to 354 mV rms. The AGC bias represents a calibrated rms
measure of the received signal strength (RSSI). Since in AGC
mode the output signal is forced to the 354 mV rms setpoint
(−9.02 dBV rms), Equation 2 can be recast to express the
strength of the received signal, V
IN-RMS
, in terms of the AGC
bias V
DETO
.
V
IN − RMS
(dBV rms) = 54.02 + 50 × V
DETO
(4)
where −54.02 dBV rms = −45 dB − 9.02 dBV rms.
For small changes in input signal level, V
DETO
responds with a
characteristic single-pole time constant, τ
AGC
, which is
proportional to C
AGC
.
τ
AGC
(μs) = 10 × C
AGC
(nf)
(5)
where the internal 5 pF capacitor is lumped with the external
capacitor to give C
AGC
.
AD8367
Rev. A | Page 14 of 24
APPLICATIONS
The AD8367 can be configured either as a VGA whose gain
is controlled externally through the GAIN pin or as an AGC
amplifier, using a supply voltage of 2.7 V to 5.5 V. The supply
to the VPSO and VPSI pins should be decoupled using a low
inductance, 0.1 μF surface-mount, ceramic capacitor as close
as possible to the device. Additional supply decoupling can
be provided by a small series resistor. A 10 nF capacitor from
Pin DECL to Pin OCOM is recommended to decouple the
output reference voltage.
INPUT AND OUTPUT MATCHING
The AD8367 is designed to operate in a 200 Ω impedance
system. The output amplifier is a low output impedance voltage
buffer with a 50 Ω damping resistor to desensitize it from load
reactance and parasitics. The quoted performance includes the
voltage division between the 50 Ω resistor and the 200 Ω load.
The AD8367 can be reactively matched to an impedance other
than 200 Ω by using traditional step-up and step down
matching networks or high quality transformers.
Table 4 lists
the 50 Ω S-parameters for the AD8367 at a V
GAIN
= 750 mV.
Figure 32 illustrates an example where the AD8367 is matched
to 50 Ω at 140 MHz. As shown in the Smith Chart, the input
matching network shifts the input impedance from Z
IN
to 50 Ω
with an insertion loss of <2 dB over a 5 MHz bandwidth. For
the output network, the 50 Ω load is made to present 200 Ω to
the AD8367 output.
Table 5 provides the component values
required for 50 Ω matching at several frequencies of interest.
When added loss and noise can be tolerated, a resistive pad can
be used to provide broadband, near-matched impedances at the
device terminals and the terminations.
Minimum-loss, L-pad networks are used on the evaluation
board (see
Figure 45) to allow easy interfacing to standard
50 Ω test equipment. Each pad introduces an 11.5 dB power
loss (5.5 dB voltage loss).
1
0.3333
–0.3333
–1
–3
3
0.3333 1 3
Z
IN
R
SOURCE
SERIES L
SHUNT C
02710-032
Z
IN
Z
IN
XS
IN
100nH
Z
LOAD
Z
OUT
XS
OUT
13pF
C
AC
0.1μF
R
SOURCE
50Ω
R
LOAD
50Ω
XP
OUT
120nH
V
S
XP
IN
8.2pF
AD8367
f
C
= 140MHz, Z
IN
= 197 – j34.2, R
SOURCE
= 50Ω
Figure 32. Reactive Matching Example for f = 140 MHz
Table 4. S-Parameters for 200 Ω System for V
S
= 5 V and V
GAIN
= 0.75 V
Frequency (MHz) S11 S21 S12 S22
10
0.04 −43.8° 41.1 178.8° 0.0003 76.1° 0.56 −179.3°
70
0.09 −81.5° 43.6 163.4° 0.0002 63.7° 0.55 +176.1°
140
0.17 −103.4° 48.0 141.4° 0.0009 130.8° 0.56 +170.2°
190
0.21 −111.7° 47.5 124.0° 0.0017 96.8° 0.54 +166.5°
240
0.26 −103.8° 48.3 107.6° 0.0018 113.5° 0.48 +164.6°
Table 5. Reactive Matching Components for a 50 Ω System where R
SOURCE
= 50 Ω, R
LOAD
= 50 Ω
Frequency (MHz) XS
IN
XP
IN
(pF) XS
OUT
(pF) XP
OUT
10 1.5 μH 120 180 1.8 μH
70 220 nH 15 27 270 nH
140 100 nH 8.2 13 120 nH
190 82 nH 2.7 10 100 nH
240 68 nH 1.5 7 82 nH

AD8367ARUZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers 500 MHz 45 dB Linear-in-dB
Lifecycle:
New from this manufacturer.
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