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AD8367ARUZ

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AD8367
Rev. A | Page 15 of 24
VGA OPERATION
The AD8367 is a general-purpose VGA suitable for use in a
wide variety of applications where voltage control of gain is
needed. While having a 500 MHz bandwidth, its use is not
limited to high frequency signal processing. Its accurate,
temperature- and supply-stable linear-in-dB scaling is
valuable wherever it is important to have a more dependable
response to the control voltage than is usually offered by VGAs
of this sort. For example, there is no preclusion to its use in
speech-bandwidth systems.
Figure 33 shows the basic connections. The C
HP
capacitor at
Pin HPFL can be used to alter the high-pass corner frequency of
the signal path and is associated with the offset control loop that
eliminates the inherent variation in the internal dc balance of the
signal path as the gain is varied (offset ripple). This frequency
should be chosen to be about a decade below the lowest frequency
component of the signal. If made much lower than necessary, the
offset loop is not able to track the variations that occur when there
are rapid changes in V
GAIN
. The control of offset is important even
when the output is ac-coupled because of the potential reduction of
the upper and lower voltage range at this pin.
However, in many applications these components are
unnecessary because an internal network provides a default
high-pass corner of about 500 kHz. For C
HP
= 1 nF, the
modified corner is at ~10 kHz; it scales downward with
increasing capacitance.
Figure 20 shows representative
response curves for the indicated component values.
02710-033
AD8367
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
GAIN
5
VOUT
10
DETO
6
DECL
9
ICOM
7
OCOM
8
V
GAIN
VOUT
V
IN
C5
10nF
C1
1μF
C4
0.1μF
C
HP
10nF
R
HP
100Ω
R6
4.7Ω
R5
4.7Ω
V
P
C3
0.1μF
C2
0.1μF
Figure 33. Basic Connections for Voltage Controlled Gain Mode
MODULATED GAIN MODE
The AD8367 can be used as a means of modulating the signal
level. Keep in mind, however, that the gain is a nonlinear
(exponential) function of V
GAIN
; thus, it is not suitable for
normal amplitude-modulation functions. The small signal
bandwidth of the gain interface is ~5 MHz, and the slew rate
is of the order of ±500 dB/μs. During gain slewing from close
to minimum to maximum gain (or vice versa), the internal
interpolation processes in an X-AMP-based VGA rapidly
scan the full range of gain values. The gain and offset ripple
associated with this process can cause transient disturbances
in the output. Therefore, it is inadvisable to use high amplitude
pulse drives with rise and fall times below 200 ns.
AGC OPERATION
The AD8367 can be used as an AGC amplifier, as shown in
Figure 34. For this application, the accurate internal, square-law
detector is employed. The output of this detector is a current
that varies in polarity, depending on whether the rms value of
the output is greater or less than its internally-determined
setpoint of 354 mV rms. This is 1 V p-p for sine-wave signals,
but the peak amplitude for other signals, such as Gaussian
noise, or those carrying complex modulation, is invariably
somewhat greater. However, for all waveforms having a crest
factor of <5, and when using a supply voltage of 4.5 V to 5.5 V,
the rms value is correctly measured and delivered at V
OUT
.
When using lower supplies, the rms value of V
OUT
is unaffected
(the setpoint is determined by a band gap reference), but the
peak crest factor capacity is reduced.
The gain pin is connected to the base of a transistor internally
and thus requires only 1 μA of current drive. The output of the
detector is delivered to Pin DETO. The detector can source up
to 60 μA and can sink up to 11 μA. For a sine-wave output
signal, and under conditions where the AGC loop is settled, the
detector output also takes the form of a sine-wave, but at twice
the frequency and having a mean value of 0. If the input to the
amplifier increases, the mean of this current also increases and
charges the external loop filter capacitor, C
AGC
, toward more
positive voltages. Conversely, a reduction in V
OUT
below the
setpoint of 354 mV rms causes this voltage to fall toward
ground. The capacitor voltage is the AGC bias; this can be
used as a received signal strength indicator (RSSI) output
and is scaled exactly as V
GAIN
, that is, 20 mV/dB.
02710-034
AD8367
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
GAIN
5
VOUT
10
DETO
6
DECL
9
ICOM
7
OCOM
8
V
AGC
VOUT
V
IN
C5
10nF
C
AGC
0.1μF
C1
1μF
C4
0.1μF
C
HP
10nF
R
HP
100Ω
R6
4.7Ω
R5
4.7Ω
V
P
C3
0.1μF
C2
0.1μF
Figure 34. Basic Connections for AGC Operation
A valuable feature of using a square law detector is that the
RSSI voltage is a true reflection of signal power and can be
converted to an absolute power measurement for any given
source impedance. The AD8367 can thus be employed as a
true-power meter, or decibel-reading ac voltmeter, as distinct
from its basic amplifier function.
The AGC mode of operation requires that the correct gain
direction is chosen. Specifically, the gain must fall as V
AGC
increases to restore the needed balance against the setpoint.
Therefore, the MODE pin must be pulled low. This accurate
leveling function is shown in
Figure 35, where the rms output is
AD8367
Rev. A | Page 16 of 24
held to within 0.1 dB of the setpoint for >35 dB range of
input levels.
The dynamics of this loop are controlled by C
AGC
acting in
conjunction with an on-chip equivalent resistance, R
AGC
, of
10 kΩ which form an effective time-constant T
AGC
= R
AGC
C
AGC
.
The loop thus operates as a single-pole system with a loop
bandwidth of 1/(2π T
AGC
). Because the gain control function is
linear in decibels, this bandwidth is independent of the absolute
signal level.
Figure 36 illustrates the loop dynamics for a 30 dB
change in input signal level with C
AGC
= 100 pF.
–1.2
–2.2
–2.1
–2.0
–1.9
–1.8
–1.7
–1.6
–1.5
–1.4
–1.3
–50 –40 –30 –20 –10 0 10
02710-035
PIN (dBm re 200Ω)
POUT (dBm re 200
Ω
)
Figure 35. Leveling Accuracy of the AGC Function
1.0
V
AGC
V
OUT
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 5 10 15 20 25 30 35 40
02710-036
TIME (μs)
V
ACG
(V); V
OUT
(arb)
Figure 36. AGC Response to a 32 dB Step in Input Level (f = 50 MHz)
It is important to understand that R
AGC
does not act as if in
shunt with C
AGC
. Rather, the error-correction process is that of a
true integrator, to guarantee an output that is exactly equal in
rms amplitude to the specified setpoint. For large changes in
input level, the integrating action of this loop is most apparent.
The slew rate of V
AGC
is determined by the peak output current
from the detector and the capacitor. Thus, for a representative
value of C
AGC
= 3 nF, this rate is about 20 V rms or 10 dB/μs,
while the small-signal bandwidth is 1 kHz.
Most AGC loops incorporating a true error-integrating
technique have a common weakness. When driven from an
increasingly larger signal, the AGC bias increases to reduce the
gain. However, eventually the gain falls to its minimum value,
for which further increase in this bias has no effect on the gain.
That is, the voltage on the loop capacitor is forced progressively
higher because the detector output is a current, and the AGC
bias is its integral. Consequently, there is always a precipitous
increase in this bias voltage when the input to the AD8367
exceeds that value that overdrives the detector, and because the
minimum gain is −2.5 dB, that happens for all inputs 2.5 dB
greater than the setpoint of ~350 mV rms. If possible, the user
should ensure that this limitation is preserved, preferably with a
guard-band of 5 dB to 10 dB below overload
In some cases, if driven into AGC overload, the AD8367
requires unusually long times to recover; that is, the voltage
at DETO remains at an abnormally high value and the gain is at
its lowest value. To avoid this situation, it is recommended that
a clamp be placed on the DETO pin, as shown in
Figure 37.
02710-037
AD8367
1 14
2 13
3 12
MODE
4 11
GAIN
5 10
DETO
6 9
ICOM
7 8
RB
RA
C
AGC
0.1μF
V
AGC
Q1
2N2907
0.5V
+V
S
Figure 37. External Clamp to Prevent AGC Overload.
The resistive divider network, RA and RB, should be designed
such that the base of Q1 is driven to 0.5 V.
MODIFYING THE AGC SETPOINT
If an AGC setpoint other than the internal one is desired, an
external detector must be used.
Figure 38 shows a method
that uses an external true-rms detector and error integrator to
operate the AD8367 as a closed-loop AGC system with a user-
settable operating level.
The AD8361 (U2) produces a dc output level that is
proportional to the rms value of its input, taken as a sample
of the AD8367 (U1) output. This dc voltage is compared to
an externally-supplied setpoint voltage, and the difference is
integrated by the AD820 (U3) to form the gain control voltage
that is applied to the GAIN input of the AD8367 through the
divider composed of R4 and R5. This divider is included in
order to minimize overload recovery time of the loop by having
the integrator saturate at a point that only slightly overdrives the
gain control input of the AD8367. The scale factor at V
AGC
is
influenced by the values of R4 and R5; for the values shown, the
factor is 86 mV/dB.
AD8367
Rev. A | Page 17 of 24
0
2710-038
VOUT
10
DECL
9
OCOM
8
C5
10nF
GAIN
5
DETO
6
ICOM
7
V
g
R5
10kΩ
AD8367
U1
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
INPUT
J1
10nF
R6
57.6Ω
C
HP
10nF
R
HP
100Ω
V
AGC
AD820
U3
2
3
6
4
7
V
SET
5V
0.1μF
R3
82kΩ
20pF
C1
3.3nF
AD8361
U2
PWDN
4
COMM
5
RFIN
3
FLTR
6
IREF
2
VRMS
7
VPOS
1
SREF
8
R2
150kΩ
R4
33kΩ
R1
200kΩ
10nF
10nF
0.1μF
2.2
Ω
12kΩ
C2
0.27μF
Vrms
V
OUT
INTO A
200Ω LOAD
5V
Figure 38. Example of Using an External Detector to Form an AGC Loop
Note that in this circuit the AD8367’s MODE pin must be
pulled high to obtain correct feedback polarity because the
integrator inverts the polarity of the feedback signal.
The relationship between the setpoint voltage and the rms
output voltage of the AD8367 is
(
)
7.5225
225
×
+
×=
−
R1
VV
SETRMSOUT
(6)
where 225 is the input resistance of the AD8361 and 7.5 is its
conversion gain. For R1 = 200 Ω, this reduces to V
OUT –RMS
= V
SET
× 0.25.
Capacitor C2 sets the averaging time for the rms detector. This
should be made long enough to provide sufficient smoothing of
the detector’s output in the presence of the modulation on the
RF signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p
at the AD8361’s output is a reasonable value. A considerably
longer time constant needlessly lowers the AGC bandwidth,
while a short time constant can degrade the accuracy of the
true-rms measurement process. Components C1, R2, and R3
set the control loop’s bandwidth and stability. The maximum
stable loop bandwidth is limited by the rms detector’s averaging
time constant as previously discussed.
For an input signal consisting of a 4.096 MS/s QPSK modulated
carrier, the relationship between V
SET
and the output power for
this setup is shown in
Figure 39. The exponential shape reflects
the linear-in-magnitude response of the AD8361. The adjacent
channel power ratio (ACPR) as a function of output power is
illustrated in
Figure 40. The minima occur where the distortion
and integrated noise powers cross over.
The component values shown in
Figure 38 were chosen for a
64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz.
The response time of the loop as shown is roughly 5 ms for
an abrupt input level change of 40 dB.
Figure 41 shows the
dynamic performance of the loop with a step-modulated
CW signal applied to the input for a V
SET
of about 1 V.
For a linear-in-dB response, detectors such as the AD8318 or
the AD8362 can be used in place of the AD8361.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–20 1050–5–10–15
02710-039
V
SET
(V)
10MHz
380MHz
POUT (dBm INTO 200Ω)
Figure 39. AGC Setpoint Voltage vs. Output Power
(QPSK: 4.096 MS/s; α = 0.22; 1 User)
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AD8367ARUZ

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Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers 500 MHz 45 dB Linear-in-dB
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