IRFR4105ZTRR

IRFR/U4105Z
www.irf.com 7
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) = DT/ Z
thJC
I
av
=
2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
A
v
a
l
a
n
c
h
e
C
u
r
r
e
n
t
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starting T
J
, Junction Temperature (°C)
0
5
10
15
20
25
30
E
A
R
,
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
TOP Single Pulse
BOTTOM 1% Duty Cycle
I
D
= 18A
IRFR/U4105Z
8 www.irf.com
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
IRFR/U4105Z
www.irf.com 9
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
6.22 (.245)
5.97 (.235)
- B -
3X
0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
4.57 (.180)
2.28 (.090)
2X
1.14 (.045)
0.76 (.030)
1.52 (.060)
1.15 (.045)
1.02 (.040)
1.64 (.025)
5.46 (.215)
5.21 (.205)
1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
10.42 (.410)
9.40 (.370)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
EXAMPLE:
LOT CODE 9U1P
T HIS IS AN IRFR120
WITH ASSEMBLY
WE E K = 16
DAT E CODE
YEAR = 0
LOGO
RECTIFIER
INT ERNATIONAL
AS S E MB L Y
LOT CODE
016
IRFU120
9U 1P
Notes: T his part marking information applies to devices produced before 02/26/2001
INT ERNATIONAL
LOGO
RECTIFIER
3412
IRFU120
916A
LOT CODE
AS S E MB L Y
EXAMPLE:
WITH ASSEMBLY
T HIS IS AN IRFR120
YE AR 9 = 1999
DAT E CODE
LINE A
WE E K 16
IN THE ASSEMBLY LINE "A"
AS SEMBLED ON WW 16, 1999
L OT CODE 1234
PART NUMBER
Notes : T his part marking information applies to devices produced after 02/26/2001

IRFR4105ZTRR

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
MOSFET N-CH 55V 30A DPAK
Lifecycle:
New from this manufacturer.
Delivery:
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