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NLV14521BDG

P1-P3P4-P6P7-P8
MC14521B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(Note 6)
Max Unit
Output Rise and Fall Time (Counter Outputs)
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q18
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 4415 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 1667 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 1275 ns
Clock to Q24
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 5915 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 2167 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 1675 ns
t
PHL
, t
PLH
5.0
10
15
−
−
−
4.5
1.7
1.3
9.0
3.5
2.7
ms
5.0
10
15
−
−
−
6.0
2.2
1.7
12
4.5
3.5
Propagation Delay Time
Reset to Q
n
t
PHL
= (1.7 ns/pF) C
L
+ 1215 ns
t
PHL
= (0.66 ns/pF) C
L
+ 467 ns
t
PHL
= (0.5 ns/pF) C
L
+ 350 ns
t
PHL
5.0
10
15
−
−
−
1300
500
375
2600
1000
750
ns
Clock Pulse Width t
WH(cl)
5.0
10
15
385
150
120
140
55
40
−
−
−
ns
Clock Pulse Frequency f
cl
5.0
10
15
−
−
−
3.5
9.0
12
2.0
5.0
6.5
MHz
Clock Rise and Fall Time t
TLH
, t
THL
5.0
10
15
−
−
−
−
−
−
15
5.0
4.0
ms
Reset Pulse Width t
WH(R)
5.0
10
15
1400
600
450
700
300
225
−
−
−
ns
Reset Removal Time t
rem
5.0
10
15
30
0
– 40
–200
–160
–110
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
V
DD
V
DD
V
DD
V
SS
V
SS
Q18
Q19
Q20
Q21
Q22
Q23
Q24
C
L
C
L
C
L
C
L
C
L
C
L
C
L
I
D
IN 2
R
500 mF
0.01 mF
CERAMIC
20 ns 20 ns
V
DD
0 V
V
in
50% DUTY CYCLE
90%
10%
50%
MC14521B
http://onsemi.com
5
Figure 2. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
Q18
Q19
Q20
Q21
Q22
Q23
Q24
IN 2
R
V
DD
V
DD
′
V
SS
V
SS
′
C
L
C
L
C
L
C
L
C
L
C
L
C
L
V
DD
20 ns 20 ns 20 ns
10%
50%
90%
10%
50%
90%
IN 2
Q
n
t
PLH
t
PHL
t
TLH
t
THL
t
WL
t
WH
Characteristic
500 kHz
Circuit
50 kHz
Circuit
Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, R
S
500
1.0
50
6.2
kHz
kW
External Resistor/Capacitor Values
R
o
C
T
C
S
47
82
20
750
82
20
kW
pF
pF
Frequency Stability
Frequency Change as a Function
of V
DD
(T
A
= 25_C)
V
DD
Change from 5.0 V to 10 V
V
DD
Change from 10 V to 15 V
Frequency Change as a Function
of Temperature (V
DD
= 10 V)
T
A
Change from – 55_C to + 25_C
MC14521 only
Complete Oscillator*
T
A
Change from +25_C to+125_C
MC14521 only
Complete Oscillator*
+ 6.0
+ 2.0
– 4.0
+ 100
– 2.0
– 160
+ 2.0
+ 2.0
– 2.0
+ 120
– 2.0
– 560
ppm
ppm
ppm
ppm
ppm
ppm
*Complete oscillator includes crystal, capacitors, and resistors.
Figure 4. Typical Data for Crystal Oscillator Circuit
Figure 3. Crystal Oscillator Circuit
V
DD
V
DD
V
DD
′
V
SS
V
SS
′
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
IN 1
IN 2
R
R*
R*
C
S
C
T
R
o
18 M
*Optional for low power operation,
10 kW ≤ R ≤ 70 kW.
MC14521B
http://onsemi.com
6
Figure 5. RC Oscillator Stability Figure 6. RC Oscillator Frequency as a
Function of R
TC
and C
-55 -25 0 25 50 75 100 125
8.0
4.0
0
-4.0
-8.0
-12
-16
FREQUENCY DEVIATION (%)
T
A
, AMBIENT TEMPERATURE (°C), DEVICE ONLY
TEST CIRCUIT
FIGURE 7
V
DD
= 15 V
10 V
5.0 V
R
TC
= 56 kW,
C = 1000 pF
R
S
= 0, f = 10.15 kHz @ V
DD
= 10 V, T
A
= 25°C
R
S
= 120 kW, f = 7.8 kHz @ V
DD
= 10 V, T
A
= 25°C
{
f, OSCILLATOR FREQUENCY (kHz)
100
50
20
10
5.0
1.0
2.0
0.1
0.2
0.5
1.0 k 10 k 100 k 1.0 m
0.0001 0.001 0.01 0.1
R
TC
, RESISTANCE (OHMS)
C, CAPACITANCE (mF)
V
DD
= 10 V
f AS A FUNCTION
OF R
TC
(C = 1000 pF)
(R
S
≈ 2R
TC
)
TEST CIRCUIT
FIGURE 7
f AS A FUNCTION
OF C
(R
TC
= 56 kW)
(R
S
= 120 k)
Figure 7. RC Oscillator Circuit Figure 8. Functional Test Circuit
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
IN 1
IN 2
R
V
DD
V
DD
′
V
SS
V
SS
′
V
DD
R
S
R
TC
C
Q18
Q19
Q20
Q21
Q22
Q23
Q24
OUT 1
OUT 2
IN 1
IN 2
R
V
DD
′
V
DD
V
SS
V
SS
PULSE
GENERATOR
FUNCTIONAL TEST SEQUENCE
A test function (see Figure 8) has been included
for the reduction of test time required to exercise a
ll
24 counter stages. This test function divides the
counter into three 8−stage sections, and 255
counts are loaded in each of the 8−stage section
s
in parallel. All flip−flops are now at a logic “1”. The
counter is now returned to the normal 24−stages in
series configuration. One more pulse is entered into
Input 2 (In 2) which will cause the counter to ripple
from an all “1” state to an all “0” state.
Inputs Outputs Comments
Reset In 2 Out 2 V
SS
′ V
DD
′ Q18
thru
Q24
Counter is in three 8−stage sections
in parallel mode Counter is reset. In 2
and Out 2 are connected together.
1 0 0
V
DD
GND
GND
V
DD
0
0
1 1 First “0” to “1” transition on In 2,
Out 2 node.
0
1
−
−
−
0
1
−
−
−
255 “0” to “1” transitions are clocked
into this In 2, Out 2 node.
1 1 1
The 255th “0” to “1” transition.
0
0
0
0
1
1
1 0 1
Counter converted back to 24−stages
in series mode.
1 0 1
Out 2 converts back to an output.
0 1 0
Counter ripples from an all “1” state
to an all “0” stage.
P1-P3P4-P6P7-P8

NLV14521BDG

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Buy NLV14521BDG
Manufacturer:
ON Semiconductor
Description:
Multipliers / Dividers 24STAGE FREQUENCY DIVIDER
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