LTC6912
22
6912fa
SNR from an amplifier is the ratio of input level to input-
referred noise, and can be 108dB with the LTC6912 family
at unity gain.
Construction and Instrumentation Cautions
Electrically clean construction is important in applications
seeking the full dynamic range of the LTC6912 family of
dual amplifiers. It is absolutely critical to have AGND either
AC bypassed or wired directly using the shortest possible
wiring, to a low impedance ground return for best channel-
to-channel isolation. Short, direct wiring minimizes para-
sitic capacitance and inductance. High quality supply
bypass capacitors of 0.1µF near the chip provide good
APPLICATIO S I FOR ATIO
WUUU
decoupling from a clean, low inductance power source.
But several centimeters of wire (i.e., a few µH of induc-
tance) from the power supplies, unless decoupled by
substantial capacitance (>10µF) near the chip, can create
a parasitic high-Q LC resonant circuit in the hundreds of
kHz range in the chip’s supplies or ground reference. This
may impair circuit performance at those frequencies. A
compact, carefully laid out printed circuit board with a
good ground plane makes a significant difference in mini-
mizing distortion. Finally, equipment to measure perfor-
mance can itself introduce distortion or noise floors.
Checking for these limits with wired shorts from INA to
OUTA and INB to OUTB in place of the chip is a prudent
routine procedure.
TYPICAL APPLICATIO
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Low Noise AC Amplifier with Programmable Gain and
Bandwidth
Analog data acquisition can exploit band limiting as well as
gain to suppress unwanted signals or noise. Tailoring an
analog front end to both the level and bandwidth of each
source maximizes the resulting SNR. Figure 7 shows a
block diagram for a low noise amplifier with gain and
bandwidth independently programmable over a 100:1
range. Channels A and B of the LTC6912-1 are used to
independently control the gain and bandwidth respec-
tively over a 100:1 range. The LT1884 dual op amp forms
an integrating lowpass loop with capacitor C2 to set the
programmable upper corner frequency. The LT1884 also
supports rail-to-rail output swings over the total supply
voltage range of 2.7V to 10.5V. AC coupling through
capacitor C1 establishes a fixed low frequency corner of
1Hz, which can be adjusted by changing C1. Alternatively,
shorting C1 makes the amplifier DC coupled. If DC gain is
not needed, the AC coupling cap C1 serves to suppress
several error sources: any shift in DC levels, low frequency
noise, and DC offset voltages (not including the LT1884’s
low internal offset).
Figure 7. Block Diagram of an AC Amplifier with Programmable Gain and Bandwidth
+
+
V
IN
V
OUT
GAINA
GAINB
C1
10µF
C2
1µF
R1
15.8k
R2
15.8k
1M
R
R
1/2 LT1884
1/2 LT1884
1/2 LT1884
LTC6912-1
CHANNEL A
LTC6912-1
CHANNEL B
GAIN
CONTROL
PGA
BANDWIDTH
CONTROL
PGA
V
OUT
= GAINA V
IN
R2
R1
6912 F07
INA OUTA
INB OUTB
1
2πR1C1
1
R2
GAINB
2π (
)
C2
–3dB BANDWIDTH RANGE IS FROM TO
LTC6912
23
6912fa
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
0.25 ± 0.05
3.30 ±0.10
(2 SIDES)
16
127
0.50
BSC
PIN 1
NOTCH
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0603
0.25 ± 0.05
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.70 ±0.05
(2 SIDES)2.20 ±0.05
0.50
BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE OUTLINE
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PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
12
3
4
5
6
7
8
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16
15
14
13
.189 – .196*
(4.801 – 4.978)
12 11 10
9
.016 – .050
(0.406 – 1.270)
.015
± .004
(0.38 ± 0.10)
× 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ± .0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6912
24
6912fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT/LT 1005 REV A • PRINTED IN USA
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U
TYPICAL APPLICATIO
INA
AGND
INB
1µF
0.1µF
CHANNEL A
INPUT
CHANNEL B
INPUT
V
OUT
(TO ADC)
OUT A
OUT B
LTC6912-X
V
+
V
+
V
SHDN
CS/LD
DATA
CLK
SHDN
CS/LD
D
IN
5
6
7
8
10
9
DGND
D
OUT
2
12 14
3
4
15
13
CHB CHA
3-WIRE
SPI
INTERFACE
6912 TA02
MUX OPERATION: IF THE LOWER NIBBLE (Q3, Q2, Q1, Q0) IS (1, 0, 0, 0) THEN OUTA IS IN
TRI-STATE AND THE UPPER NIBBLE (Q7, Q6, Q5, Q4) CONTROLS THE ACTIVE CHANNEL B.
IF THE UPPER NIBBLE IS (1, 0, 0, 0) THEN OUTB IS IN TRI-STATE
AND THE LOWER NIBBLE CONTROLS ACTIVE CHANNEL A.
A 2:1 PGA MUX

LTC6912HGN-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers 2x Progmable Gain Amps w/ Serial Dig Int
Lifecycle:
New from this manufacturer.
Delivery:
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